Thin film transistor array panel and manufacture thereof

1. A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line and a pixel electrode on a substrate;

forming a gate insulating layer on the gate line;

forming a data line including a source electrode and a drain electrode on the gate insulating layer;

forming an interlayer insulating layer covering the data line and the pixel electrode;

forming a first opening in the interlayer insulating layer;

forming an organic semiconductor in the first opening;

forming a passivation layer on the organic semiconductor and the interlayer insulating layer; and

forming a second opening in the interlayer insulating layer to expose the pixel electrode after forming the passivation layer.

2. The method of claim 1 further comprising forming a protecting member on the organic semiconductor.

3. The method of claim 1 , wherein the second opening is formed by etching the interlayer insulating layer using the passivation layer as an etch mask.

4. The method of claim 1 , wherein the gate line and the pixel electrode are formed by depositing a first layer made of a transparent conductive material and a second layer made of a metallic material.

5. The method of claim 4 , wherein forming the data line and the drain electrode includes:

sequentially depositing a third layer made of a transparent conductive material and a fourth layer made of a metallic material;

forming a photoresist pattern including a first portion and a second portion that is thinner than the first portion;

etching the fourth layer and the third layer using the photoresist pattern as an etch mask; and

etching the fourth layer using the first portion of the photoresist pattern as an etch mask.

6. The method of claim 5 , wherein the second layer of the pixel electrode is etched when etching the fourth layer using the first portion of the photoresist pattern.

7. The method of claim 6 , wherein the second portion of the photoresist pattern is aligned on the source electrode and the drain electrode.

8. The method of claim 1 , wherein the organic semiconductor is formed by an ink-jet method.

9. A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line including a gate electrode on a substrate;

forming a gate insulating layer covering the gate line;

forming a data line including a source electrode and a pixel electrode on the gate insulating layer;

forming an interlayer insulating layer covering the data line and the pixel electrode;

forming a first opening in the interlayer insulating layer;

forming an organic semiconductor in the first opening;

forming a passivation layer on the organic semiconductor and the interlayer insulating layer; and

forming a second opening in the interlayer insulating layer to expose the pixel electrode after forming the passivation layer.

10. The method of claim 1 further comprising forming a protecting member on the organic semiconductor.

11. The method of claim 10 , wherein the second opening is formed by etching the interlayer insulating layer using the passivation layer as an etch mask.

12. The method of claim 10 , wherein forming the data line and the pixel electrode includes:

sequentially depositing a first layer made of a transparent conductive material and a second layer made of a metal material; and

removing the portion of the second layer.

13. The method of claim 10 , wherein the organic semiconductor is formed by an ink-jet method.