IP Library Granted Patent US 8,999,058
Granted Patent B2
US 8,999,058 · App. 12/774,667 · Granted Apr 7, 2015

High-productivity porous semiconductor manufacturing equipment

Inventors: George D. Kamian (Scotts Valley, CA); Somnath Nag (Saratoga, CA); Subbu Tamilmani (San Jose, CA); Mehrdad M. Moslehi (Los Altos, CA); Karl-Josef Kramer (San Jose, CA); Takao Yonehara (Kanagawa, JP)
Assignee: Solexel, Inc.
C25D11/32H01L31/1892C25D17/001C25D17/06C25D11/005Y02E10/50
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Quick Facts
Patent No.
US 8,999,058
App. No.
12/774,667
Granted
Apr 7, 2015
Kind
B2
Abstract

This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further the disclosure is applicable to the general fields of Photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

Claims (23)

1. An apparatus for producing a layer of porous semiconductor on a plurality of semiconductor wafers, comprising:

a first electrode and a second electrode for producing an electrical current, wherein said first electrode and said second electrode are operable to alternate or modulate current and voltage polarity at least one cycle after a predetermined period of time;

a plurality of semiconductor wafers in a stacked arrangement, wherein each said semiconductor wafer is held in place by a perimeter wafer seal disposed around a perimeter of said semiconductor wafer, and wherein said stacked arrangement may be at any angle relative to vertical;

an electrolyte supply for providing an electrolyte to said apparatus; and

a plurality of electrolyte channels or electrolyte compartments disposed between each of said plurality of semiconductor wafers for providing said electrolyte to at least a surface of each said semiconductor wafer and for removing a gas from said surface.

2. The apparatus of claim 1 , wherein said plurality of semiconductor wafers comprises a plurality of silicon wafers.

3. The apparatus of claim 1 , wherein said plurality of semiconductor wafers comprises either a plurality of square semiconductor wafers or a plurality of pseudo-square semiconductor wafers.

4. The apparatus of claim 1 , wherein said plurality of semiconductor wafers comprises a plurality of substantially circular semiconductor wafers.

5. The apparatus of Claim 1 , wherein said first electrode and said second electrode are operable to produce said electrical current at a plurality of predetermined levels for producing a plurality of layers having distinct porosities.

6. The apparatus of claim 5 , wherein said plurality of predetermined levels comprises a set of discrete levels for multi-layer porosity.

7. The apparatus of claim 5 , wherein said plurality of predetermined levels comprises a continuum of levels for graded porosity.

8. The apparatus of claim 1 , wherein each said wafer seal comprises a conforming edge seal for adapting to a range of wafer diameters and wafer thicknesses.

9. An apparatus for producing a layer of porous semiconductor on a plurality of semiconductor wafers, comprising:

a first electrode and a second electrode for producing an electrical current, wherein said first electrode and said second electrode are operable to alternate or modulate current and voltage polarity at least one cycle after a predetermined period of time;

a plurality of arrays of semiconductor wafers in a stacked arrangement, wherein each said semiconductor wafer is held in place by a perimeter wafer seal disposed around a perimeter of said semiconductor wafer, and wherein said stacked arrangement may be at any angle relative to vertical;

an electrolyte supply for providing an electrolyte to said apparatus; and

a plurality of electrolyte channels or electrolyte compartments disposed between each of said plurality of arrays of semiconductor wafers for providing said electrolyte to at least a surface of each said semiconductor wafer and for removing a gas from said surface.

10. The apparatus of claim 9 , wherein each said semiconductor wafer of said plurality of arrays of semiconductor wafers comprises either a square semiconductor wafer or a pseudo-square semiconductor wafer.

11. The apparatus of claim 9 , wherein each said semiconductor wafer of said plurality of arrays of semiconductor wafers comprises a substantially circular semiconductor wafer.

12. The apparatus of Claim 9 , wherein said first electrode and said second electrode are operable to produce said electrical current at a plurality of predetermined levels for producing a plurality of layers having distinct porosities.

13. The apparatus of claim 12 , wherein said plurality of predetermined levels comprises a set of discrete levels for multi-layer porosity.

14. The apparatus of claim 12 , wherein said plurality of predetermined levels comprises a continuum of levels for graded porosity.

15. The apparatus of claim 9 , wherein each said wafer seal comprises a conforming edge seal for adapting to a range of wafer diameters and wafer thicknesses.

Assignments (11)
SECURITY INTEREST Recorded Nov 12, 2024
From: TRUTAG TECHNOLOGIES, INC.
To: KUMUKAHI HOLDINGS, INC.
Reel/Frame 069240/0893 →
NON-RECOURSE ASSIGNMENT OF INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Oct 1, 2024
From: FIRST-CITIZENS BANK & TRUST COMPANY
To: KUMUKAHI HOLDINGS, INC.
Reel/Frame 069083/0367 →
SECURITY INTEREST Recorded Dec 26, 2023
From: TRUTAG TECHNOLOGIES, INC.
To: FIRST-CITIZENS BANK & TRUST COMPANY
Reel/Frame 066140/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2018
From: BEAMREACH-SOLEXEL ASSETS, LLC
To: TRUTAG TECHNOLOGIES, INC.
Reel/Frame 046279/0981 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2018
From: OB REALTY, LLC
To: BEAMREACH-SOLEXEL ASSETS LLC
Reel/Frame 046493/0343 →
ASSIGNMENT OF LOAN DOCUMENTS Recorded Sep 29, 2017
From: OPUS BANK
To: OB REALTY, LLC
Reel/Frame 044062/0383 →
CHANGE OF NAME Recorded Jul 28, 2017
From: SOLEXEL, INC.
To: BEAMREACH SOLAR, INC.
Reel/Frame 043367/0649 →
RECORDATION OF FORECLOSURE OF PATENT PROPERTIES Recorded Jul 27, 2017
From: OB REALTY, LLC
To: OB REALTY, LLC
Reel/Frame 043350/0822 →
CHANGE OF NAME Recorded Jul 26, 2017
From: SOLEXEL, INC.
To: BEAMREACH SOLAR, INC.
Reel/Frame 043342/0439 →
SECURITY INTEREST Recorded Jan 7, 2015
From: SOLEXEL, INC.
To: OPUS BANK
Reel/Frame 034731/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2010
From: MOSLEHI, MEHRDAD M; KAMIAN, GEORGE D.; TAMILMANI, SUBBU; NAG, SOMNATH; KRAMER, KARL-JOSEF; YONEHARA, TAKAO
To: SOLEXEL, INC.
Reel/Frame 025153/0391 →
Continuity (2)
Provisional Application 61175535 · May 5, 2009
Related Publication 20110030610A1 · Feb 10, 2011