Circuit arrangement with interference protection
View Patent ↗A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.
1. A blocking circuit for suppressing signal components generated by circuit blocks of an integrated circuit chip system from interference with other circuit blocks of the integrated circuit chip system, the blocking circuit configured to couple to an internal power supply providing a power signal to a first circuit block and a second circuit block of the integrated circuit chip system, the blocking circuit comprising:
at least three ports, wherein the at least three ports include:
a first port and a second port configured to couple to a supply line of the internal power supply;
a third port configured to couple to a ground line of the internal power supply; and
at least three frequency responsive admittances coupled to one or more of the at least three ports, the three or more frequency responsive admittances configured to reduce crosstalk effect by suppressing one or more signal components generated by one circuit block of the first and second circuit blocks from interference with the other circuit block; and
wherein an admittance value of at least one frequency responsive admittance of the at least three frequency responsive admittances is configured to increase in response to a decreasing frequency component of the power signal.
2. The blocking circuit of claim 1 , wherein a second frequency responsive admittance of the at least three frequency responsive admittances is configured to decrease in response to the decreasing frequency.
3. The blocking circuit of claim 2 , comprising:
a first node;
a second node coupled to the third port; and
wherein the at least three frequency responsive admittances include:
the at least one frequency responsive admittance coupled between the first port and the first node;
the second frequency responsive admittance coupled between the first node and the second port; and
a third frequency responsive admittance coupled between the first node and the second node.
4. The blocking circuit of claim 3 , wherein an admittance of the third frequency responsive admittance is configured to decrease in response to the decreasing frequency.
5. The blocking circuit of claim 4 , wherein the second node is coupled directly to the third port.
6. The blocking circuit of claim 4 , wherein the at least three ports includes a fourth port coupled to the ground line; and
wherein the blocking circuit further comprises:
a fourth frequency responsive admittance configured to couple the second node to the third port; and
a fifth frequency responsive admittance configured to couple the second node to the fourth port.
7. The blocking circuit of claim 6 , wherein an admittance of the fourth frequency responsive admittance is configured to increase in response to the decreasing frequency; and
wherein an admittance of the fifth frequency responsive admittance is configured to increase in response to the decreasing frequency.
8. The blocking circuit of claim 2 , wherein the at least three frequency responsive admittances include:
the at least one frequency responsive admittance coupled between the first port and the second port; and
the second frequency responsive admittance coupled between the first port and the third port.
9. The blocking circuit of claim 8 , including a third frequency responsive admittance directly coupled with the second port and directly coupled with the third port.
10. The blocking circuit of claim 8 , comprising a fourth port coupled to the ground line; and
a third frequency responsive admittance coupled between the second port and the fourth port.
11. The blocking circuit of claim 10 , comprising a fourth frequency responsive admittance coupled between the third port and the fourth port.
12. The blocking circuit of claim 11 , wherein an admittance of the fourth frequency responsive admittance is configured to increase with the decreasing frequency.
13. The blocking circuit of claim 11 , wherein the at least three frequency responsive admittances include:
a fifth frequency responsive admittance coupled between the first port and the fourth port; and
a sixth frequency responsive admittance coupled between the second port and the third port.
14. The blocking circuit of claim 13 , wherein an admittance of the fifth frequency responsive admittance is configured to increase in response to the decreasing frequency; and
wherein an admittance of the sixth frequency responsive admittance is configured to increase in response to the decreasing frequency.
15. An integrated circuit chip system comprising:
a first circuit block including a first frequency generator, a second circuit block including a second frequency generator, the second frequency generator configured to provide a second clock signal having a second frequency, wherein one or more circuits of the second circuit block are configured to receive the second clock signal; and
a blocking circuit configured to couple to a supply line and a ground line providing power for the first circuit block and the second circuit block, the blocking circuit comprising:
at least three ports, wherein the at least three ports include:
a first port and a second port configured to couple to a supply line of the internal power supply;
a third port configured to couple to a ground line of the internal power supply; and
at least three frequency responsive admittances coupled to one or more of the at least three ports, the three or more frequency responsive admittances configured to reduce crosstalk effect by suppressing signals generated by one circuit block of the first and second circuit blocks from interference with the other circuit block; and
wherein an admittance value of at least one frequency responsive admittance of the at least three frequency responsive admittances is configured to increase in response to a decreasing frequency component of the power signal.
16. The integrated circuit chip system of claim 15 , wherein a second frequency responsive admittance of the at least three frequency responsive admittances is configured to decrease in response to the decreasing frequency.
17. The integrated circuit chip system of claim 15 , wherein the first frequency generator is configured to provide a first clock signal having a first frequency, wherein one or more circuits of the first circuit block are configured to receive the first clock signal; and
wherein the second frequency generator configured to provide a second clock signal having a second frequency, wherein one or more circuits of the second circuit block are configured to receive the second clock signal.
18. The integrated circuit chip system of claim 15 , wherein the integrated circuit chip system is a system on chip (SoC) system.
19. The integrated circuit chip system of claim 15 , wherein the integrated circuit chip system is a Package on Package (PoP) system.