Integrated devices on a common compound semiconductor III-V wafer
View Patent ↗An integrated pair of HBT and FET transistors shares a common compound semiconductor III-V epitaxial layer. The integrated pair of transistors includes a semi-insulating substrate of a compound semiconductor III-V material, a first epitaxial structure disposed on top of the substrate, a second epitaxial structure on top of the first epitaxial structure, and a third epitaxial structure disposed on top of the second epitaxial structure. The first epitaxial structure forms a portion of the HBT transistor. A concentration profile of a first contaminant, which contributes electrical charge, decreases substantially smoothly across an interface between the semi-insulating substrate and the first epitaxial structure. In some cases, the interface is free of a second contaminant that was present, during formation of the epitaxial structures, in a chamber in which the epitaxial structures were formed.
1. An integrated pair of HBT and FET transistors sharing a common compound semiconductor III-V epitaxial layer, the integrated pair of transistors comprising:
a semi-insulating substrate of a compound semiconductor III-V material;
a first epitaxial structure disposed on top of the substrate, the first epitaxial structure forming a portion of the FET transistor;
a second epitaxial structure on top of the first epitaxial structure, the second epitaxial structure serving as the shared common compound semiconductor III-V epitaxial layer;
a third epitaxial structure disposed on top of the second epitaxial structure, the third epitaxial structure forming a portion of the HBT transistor; and
an interface between the semi-insulating substrate and the first epitaxial structure wherein a concentration profile of a first contaminant across the interface decreases substantially smoothly, wherein the first contaminant contributes electrical charge.
2. The integrated pair of transistors of claim 1 wherein the first contaminant is silicon.
3. The integrated pair of transistors of claim 1 wherein the interface is substantially free of a second contaminant that was present, during formation of the epitaxial structures, in a chamber in which the epitaxial structures were formed.
4. The integrated pair of transistors of claim 3 wherein the second contaminant is tellurium.
5. The integrated pair of transistors of claim 3 wherein the first contaminant is silicon and the second contaminant is tellurium.