Method of fabricating a TFT substrate including a data insulating layer with a contact hole overlapping a channel region

1. A method of fabricating a thin-film transistor (TFT) substrate, the method comprising:

forming a gate electrode on a pixel region of a substrate;

forming a gate insulating film on the gate electrode;

forming a semiconductor layer on the gate insulating film to overlap the gate electrode;

forming a source electrode and a spaced apart drain electrode both to overlap the semiconductor layer and thus define a channel region in the semiconductor layer where not overlapped by the source and drain electrodes; and

forming a data insulating film on the source electrode and the drain electrode; and

patterning the data insulating film such that a bottommost part of a drain contact hole formed through the data insulating film by patterning overlaps part of the channel region and the drain electrode,

wherein the bottommost part of the drain contact hole that overlaps the part of the channel region does not overlap the drain electrode; and

and forming a conductor extending to the bottommost part of the drain contact hole and making electrical contact with a sidewall part of the drain electrode that is exposed by the drain contact hole.

2. The method of claim 1 , wherein a linewidth or diameter of the drain electrode is 6 μm or less.

3. The method of claim 2 , wherein the source electrode surrounds the drain electrode.

4. The method of claim 2 , wherein the patterning of the data insulating film comprises etching the data insulating film without etching the semiconductor layer.

5. The method of claim 2 , further comprising forming a passivation layer in a region between the source electrode and the drain electrode above the semiconductor layer, wherein the passivation layer does not cover a top surface of the source electrode and a top surface of the drain electrode.

6. The method of claim 5 , wherein the passivation layer and the data insulating film are made of different materials.

7. The method of claim 5 , wherein the drain contact hole exposes the passivation layer formed on the channel region.

8. The method of claim 6 , wherein the passivation layer is silicon oxide (SiOx), and the data insulating film is silicon nitride (SiNx).

9. The method of claim 5 , wherein the forming of the passivation layer comprises stacking an insulating material on photoresist patterns, which are formed respectively and directly on the source electrode and the drain electrode, and the semiconductor layer and simultaneously exfoliating the photoresist patterns and the insulating material.