IP Library Granted Patent US 8,410,570
Granted Patent B2
US 8,410,570 · App. 12/781,489 · Granted Apr 2, 2013

Photodiode with interfacial charge control and associated process

Inventors: Jorge Regolini (Bernin, FR); Michael Gros-Jean (Grenoble, FR)
Assignees: STMicroelectronics S.A.; STMicroelectronics (Crolles 2) SAS
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Quick Facts
Patent No.
US 8,410,570
App. No.
12/781,489
Granted
Apr 2, 2013
Kind
B2
Abstract

A photodiode includes a first doped layer and a second doped layer that share a common face. A deep isolation trench has a face contiguous with the first and second doped layers. A conducting layer is in contact with a free face of the second doped layer. A protective layer is provided at an interface with the first doped layer and second doped layer. This protective layer is capable of generating a layer of negative charge at the interface. The protective layer may further be positioned within the second doped layer to form an intermediate protective structure.

Claims (55)

1. A photodiode comprising:

a first doped layer;

a second doped layer having a common face with the first doped layer;

at least one deep isolation trench having a face contiguous with the first doped layer and the second doped layer;

a conducting layer in contact with a free face of the second doped layer; and

a protective layer configured to generate a layer of negative charge at an interface between, on one side, the first and second doped layers and, on the other side, the deep isolation trench, said protective layer made from a protective material implanted with a material selected from the group consisting of F and ZrO 2 .

2. The photodiode according to claim 1 , wherein the thickness of the protective layer is between 5 nm and 20 nm.

3. The photodiode according to claim 1 , wherein the protective material is selected from the group consisting of AlF 3 , SiN/SiC, Al 2 O 3 , HfAl x O y /SiO 2 , and AlN.

4. A photodiode, comprising:

a first doped layer;

a second doped layer having a common face with the first doped layer;

at least one deep isolation trench having a face contiguous with the first doped layer and the second doped layer;

a conducting layer in contact with a free face of the second doped layer;

a protective layer configured to generate a layer of negative charge at an interface between, on one side, the first and second doped layers and, on the other side, the deep isolation trench; and

an intermediate protective layer at least partly located in the second doped layer, said intermediate protective layer configured to generate a layer of negative charge at an interface with the second doped layer.

5. A process for producing a deep isolation trench for a photodiode made from a structure comprising a first doped layer and a second doped layer sharing a common face, and a conducting layer in contact with a free face of the second doped layer, comprising:

etching at least one trench through the first doped layer and the second doped layer as far as the conducting layer;

conformally depositing in the trench a protective layer of a material providing a layer of negative charge at an interface with first and second doped layers, said material providing a layer of negative charge selected from the group consisting of AlF 3 , SiN/SiC, Al 2 O 3 and HfAl x O y /SiO 2 ; and

conformally depositing an insulator on the protective layer to fill the trench.

6. The process according to claim 5 , wherein the protective layer has a thickness of between 5 nm and 20 nm.

7. The process according to claim 5 , wherein the protective layer material is implanted with a material selected from the group consisting of F and ZrO 2 .

8. A photodiode, comprising:

a first layer of a first conductivity type;

a second layer of a second conductivity type located underneath the first layer;

an isolation trench; and

a protective layer located at an interface between the isolation trench and the first and second layers, the protective layer including doping species configured to provide a layer of negative charge at the interface, said doping species comprising an implantation material selected from the group consisting of F and ZrO 2 .

9. The photodiode of claim 8 , wherein the protective layer is made of a material selected from the group consisting of AlF 3 , SiN/SiC, Al 2 O 3 , HfAl x O y /SiO 2 , and AlN.

10. A photodiode comprising:

a first layer of a first conductivity type;

a second layer of a second conductivity type located underneath the first layer;

an isolation trench;

a protective layer located at an interface between the isolation trench and the first and second layers, the protective layer including doping species configured to provide a layer of negative charge at the interface; and

an intermediate protective layer passing through the second layer, said intermediate protective layer configured to provide a layer of negative charge within the second layer.

11. The photodiode of claim 10 , wherein the protective layer and intermediate protective layer are both made of a material selected from the group consisting of AlF 3 , SiN/SiC, Al 2 O 3 , HfAl x O y /SiO 2 , and AlN with an implantation of F and ZrO 2 .

12. A method, comprising:

forming a first doped silicon layer of a first conductivity type;

depositing an intermediate protective layer of a material providing a layer of negative charge at an interface with the first doped silicon layer;

forming a second doped silicon layer of the same first conductivity type overlying the intermediate protective layer;

forming a third doped silicon layer of a second conductivity type overlying the second doped silicon layer;

etching a trench through the second and third doped silicon layers and into at least a portion of the first doped silicon layer;

conformally depositing in the trench a protective layer of a material providing a layer of negative charge at an interface with first through third doped silicon layers; and

depositing an insulator on the protective layer to fill the trench.

13. The process of claim 12 , wherein the protective layer and intermediate protective layer are both made of a material selected from the group consisting of AlF 3 , SiN/SiC, Al 2 O 3 , HfAl x O y /SiO 2 , and AlN with an implantation of F and ZrO 2 .

14. A method, comprising:

forming a first doped silicon layer of a first conductivity type;

forming a second doped silicon layer of a second conductivity type overlying the first doped silicon layer;

etching a trench through the second doped silicon layer and into at least a portion of the first doped silicon layer;

conformally depositing in the trench a protective layer of a material providing a layer of negative charge at an interface with first and second doped silicon layers, said material providing a layer of negative charge selected from the group consisting of AlF 3 , SiN/SiC, Al 2 O 3 , and HfAl x O y /SiO 2 ; and

depositing an insulator on the protective layer to fill the trench.

15. The process of claim 14 , further comprising implanting the protective layer with a material selected from the group consisting of F and ZrO 2 .

16. The method of claim 14 further comprising:

depositing an intermediate protective layer of a material providing a layer of negative charge at an interface with the first doped silicon layer; and

forming a third doped silicon layer of the same first conductivity type overlying the intermediate protective layer and underneath the second doped silicon layer.

17. The process of claim 16 , wherein the protective layer and intermediate protective layer are both made of a material selected from the group consisting of AlF 3 , SiN/SiC, and HfAl x O y /SiO 2 .

18. The photodiode according to claim 4 , wherein the protective layer and intermediate protective layer are made of a material selected from the group consisting of AlF 3 , SiN/SiC, Al 2 O 3 , HfAl x O y /SiO 2 , and AlN with an implantation of F and ZrO 2 .

Assignments (2)
CHANGE OF NAME Recorded Feb 23, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066663/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2010
From: REGOLINI, JORGE; GROS-JEAN, MICHAEL
To: STMICROELECTRONICS S.A.; STMICROELECTRONICS (CROLLES 2) S.A.S.
Reel/Frame 024395/0858 →
Priority Claims (1)
FR 09 53288 · May 18, 2009 · national
Continuity (1)
Related Publication 20100289106A1 · Nov 18, 2010