Method of layout of pattern
View Patent ↗A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
1. A method of forming a semiconductor device, comprising:
forming a wiring layer in a semiconductor chip forming area of a semiconductor wafer, the wiring layer extending in a first direction from a top view;
forming a plurality of first dummy patterns which are placed between the wiring layer and a scribed area of the semiconductor wafer and arranged in the first direction, the plurality of first dummy patterns being placed apart from the wiring layer with a first distance in a second direction perpendicular to the first direction, the plurality of first dummy patterns having a same layer level as that of the wiring layer;
forming a second dummy pattern in the semiconductor chip forming area between the wiring layer and the plurality of first dummy patterns, the second dummy pattern continuously extending in the first direction so that the second dummy pattern intervenes between the wiring layer and each of the first dummy patterns in the second direction, the second dummy pattern being placed apart from the wiring layer with a second distance and apart from the first dummy patterns with a third distance in the second direction, the second dummy pattern having a same layer level as that of the wiring layer; and
dividing the semiconductor chip forming area along the scribed area.
2. The method as claimed in claim 1 , wherein the first dummy pattern is one of a square shape and a rectangular shape.
3. The method as claimed in claim 1 , further comprising:
forming the wiring layer so as to further extend in the second direction so that the wiring layer includes a corner portion intersecting the wiring layer extending in the first direction and the wiring layer extending in the second direction;
forming the first dummy patterns so as to be further arranged in the second direction along the wiring layer extending in the second direction; and
forming the second dummy pattern so as to further continuously extend in the second direction so that the second dummy pattern includes a corner portion that intersects the second dummy pattern extending in the first direction and the second dummy pattern extending in the second direction, so that the second dummy pattern extending in the second direction intervenes between the wiring layer extending in the second direction and each of the first dummy patterns arranged in the second direction.
4. The method as claimed in claim 1 , wherein the second dummy pattern is only provided between the wiring layer and the scribed area.
5. A method of forming a semiconductor device, comprising:
forming a wiring layer in a semiconductor chip forming area of a semiconductor wafer, the wiring layer extending in a first direction from a top view;
forming a plurality of first dummy patterns which are placed between the wiring layer and a scribed area of the semiconductor wafer and arranged in the first direction, the plurality of first dummy patterns having a same layer level as that of the wiring layer;
forming a second dummy pattern in the semiconductor chip forming area between the wiring layer and the plurality of first dummy patterns, the second dummy pattern continuously extending in the first direction so that the second dummy pattern intervenes between the wiring layer and each of the first dummy patterns in a second direction perpendicular to the first direction, the second dummy pattern having a same layer level as that of the wiring layer; and
dividing the semiconductor chip forming area along the scribed area.
6. The method as claimed in claim 5 , wherein the first dummy pattern is one of a square shape and a rectangular shape.
7. The method as claimed in claim 5 , further comprising:
forming the wiring layer so as to further extend in the second direction so that the wiring layer includes a corner portion intersecting the wiring layer extending in the first direction and the wiring layer extending in the second direction;
forming the first dummy patterns so as to be further arranged in the second direction along the wiring layer extending in the second direction; and
forming the second dummy pattern so as to further continuously extend in the second direction so that the second dummy pattern includes a corner portion that intersects the second dummy pattern extending in the first direction and the second dummy pattern extending in the second direction, so that the second dummy pattern extending in the second direction intervenes between the wiring layer extending in the second direction and each of the first dummy patterns arranged in the second direction.
8. The method as claimed in claim 5 ,
wherein the second dummy pattern is only provided between the wiring layer and the scribed area.
9. A semiconductor device, comprising:
a semiconductor substrate;
a wiring layer formed over the semiconductor substrate and extending in a first direction from a top view;
a plurality of first dummy patterns arranged in the first direction, the first dummy patterns having a same layer level as that of the wiring layer; and
a second dummy pattern placed between the wiring layer and the plurality of first dummy patterns, the second dummy pattern continuously extending in the first direction so that the second dummy pattern intervenes between the wiring layer and each of the first dummy patterns in a second direction perpendicular to the first direction, the second dummy pattern having a same layer level as that of the wiring layer.
10. The semiconductor device as claimed in claim 9 , wherein the first dummy pattern is one of square shaped and rectangular shaped.
11. The semiconductor device as claimed in claim 9 ,
wherein the wiring layer further extends in the second direction so that the wiring layer includes a corner portion that intersects the wiring layer extending in the first direction and the wiring layer extending in the second direction;
wherein the first dummy patterns are further arranged in the second direction along the wiring layer extending in the second direction,
wherein the second dummy pattern further continuously extends in the second direction so that the second dummy pattern includes a corner portion that intersects the second dummy pattern extending in the first direction and the second dummy pattern extending in the second direction, and
wherein the second dummy pattern extending in the second direction intervenes between the wiring layer extending in the second direction and each of the first dummy patterns arranged in the second direction.
12. The semiconductor device as claimed in claim 9 ,
wherein the plurality of first dummy patterns are placed apart from the wiring layer with a first distance in the second direction perpendicular to the first direction, and
wherein the second dummy pattern is placed apart from the wiring layer with a second distance and apart from the first dummy patterns with a third distance in the second direction.
13. The semiconductor device as claimed in claim 9 , wherein the second dummy pattern is provided between the wiring layer and a scribed area.
14. The semiconductor device as claimed in claim 13 , wherein the second dummy pattern is only provided between the wiring layer and the scribed area.