IP Library Granted Patent US 8,073,986
Granted Patent B2
US 8,073,986 · App. 12/782,232 · Granted Dec 6, 2011

Memory devices configured to identify an operating mode

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Quick Facts
Patent No.
US 8,073,986
App. No.
12/782,232
Granted
Dec 6, 2011
Kind
B2
Abstract

Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface by the identification circuitry. The controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.

Claims (39)

1. A memory device, comprising:

a memory module;

an interface;

identification circuitry configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface; and

a controller coupled to the memory module and the identification circuitry, wherein the controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.

2. The memory device of claim 1 , wherein the memory module is a flash memory module.

3. The memory device of claim 1 , wherein the controller is a flash memory controller.

4. The memory device of claim 1 , wherein the identification circuitry comprises encoding circuitry and sensing circuitry.

5. The memory device of claim 1 , wherein the memory device comprises a flash memory card.

6. The memory device of claim 5 , wherein the identification circuitry is physically formed on the flash memory card.

7. The memory device of claim 1 , wherein the identification circuitry is configured to receive a signal originating from a host coupled to the interface that identifies the selected operating mode.

8. The memory device of claim 7 , wherein the signal comprises an unencoded signal.

9. The memory device of claim 1 , wherein the controller is operable to configure the memory device to a preliminary operating mode before the identification circuitry identifies the selected operating mode.

10. The memory device of claim 1 , wherein the interface comprises a connector having a plurality of terminals.

11. A memory device, comprising:

a memory module;

an interface comprising a plurality of terminals for communication with a host coupled to the memory device;

identification circuitry configured to generate and to decode one or more defined sets of signals where each set of signals corresponds to a particular operating mode; and

a controller coupled to the memory module and the interface wherein the controller is operable to apply a generated set of signals to the plurality of terminals of the interface, and to configure the memory device to a particular operating mode in response to a decoded set of signals sensed at the interface after the generated set of signals are applied.

12. A memory device, comprising:

a memory module;

a first interface device comprising a plurality of terminals;

identification circuitry wherein the identification circuitry is configured to generate a first set of signals to be applied to the first interface device and to sense a second set of signals at the first interface device after the application of the first set of signals; and

a controller wherein the controller is operable to configure the memory device to a particular operating mode when the second set of signals match the first set of signals.

13. The memory device of claim 12 , wherein the identification circuitry comprises encoding circuitry and sensing circuitry.

14. The memory device of claim 12 , wherein the first set of signals corresponds to a particular predetermined code of a plurality of predetermined codes, each predetermined code corresponding to a particular operating mode of the memory device.

15. The memory device of claim 12 , wherein the memory device comprises a flash memory card and an adapter module configured to be coupled between the flash memory card and a second interface device, and where the identification circuitry is physically formed in the adapter module.

16. The memory device of claim 15 , wherein the particular operating mode is a particular operating mode of the second interface device configured to couple the memory device to a port of a host.

17. The memory device of claim 12 , wherein the first interface device comprises a plurality of input/output terminals.

18. The memory device of claim 12 , wherein the first interface device comprises a connector.

19. The memory device of claim 12 , wherein the identification circuitry is further configured to receive preencoded signals, encode the preencoded signals with the first set of signals to transform the preencoded signals to encoded signals, and sense the encoded signals as the second set of signals.

20. The memory device of claim 19 , wherein the controller is operable to configure the memory device to a preliminary operating mode before the identification circuitry encodes the preencoded signals.

21. A memory device, comprising:

a memory module;

an interface comprising a plurality of terminals;

identification circuitry comprising encoding circuitry and sensing circuitry wherein the encoding circuitry is configured to generate a first set of signals to be applied to the interface and where the sensing circuitry is configured to decode a second set of signals at the interface after the application of the first set of signals; and

a controller wherein the controller is operable to configure the memory device to a particular operating mode when the first set of signals and the second set of signals are the same.

22. The memory device of claim 21 , wherein the first set of signals corresponds to one of a set of predetermined codes where each predetermined code corresponds to a particular operating mode of the memory device.

23. The memory device of claim 21 , wherein the identification circuitry is further configured to apply and to sense a set of signals from less than all of the plurality of terminals of the interface.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
MERGER Recorded Mar 25, 2011
From: LEXAR MEDIA, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 026024/0131 →