IP Library Granted Patent US 8,344,515
Granted Patent B2
US 8,344,515 · App. 12/782,360 · Granted Jan 1, 2013

Semiconductor device

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Quick Facts
Patent No.
US 8,344,515
App. No.
12/782,360
Granted
Jan 1, 2013
Kind
B2
Abstract

A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.

Claims (34)

1. A semiconductor device, comprising:

a plurality of through vias extending through a substrate, wherein

the plurality of through vias are arranged dividedly in three or more via groups, and

each of the via groups includes three or more of the through vias that are arranged in two dimensions, and

the smallest distance between the individual through vias in each of the via groups is smaller than the smallest one of distances between an active element formed on the substrate and the plurality of through vias.

2. The semiconductor device of claim 1 , wherein

a wiring layer is formed on at least one of the first surface and the second surface opposite to the first surface of the substrate, and

at least one of the plurality of through vias and the wiring layer are electrically connected to each other.

3. The semiconductor device of claim 1 , wherein an active element is not formed in any of respective regions of the substrate where the individual via groups are disposed.

4. The semiconductor device of claim 1 , wherein the smallest distance between the individual via groups is larger than the largest distance between the individual through vias in the one of the via groups that has the smallest layout area.

5. The semiconductor device of claim 1 , wherein at least one of the via groups includes two or more of the through vias that have different potentials.

6. The semiconductor device of claim 1 , wherein at least one of the via groups includes two or more of the through vias that have the same potentials.

7. The semiconductor device of claim 6 , wherein the same signal is inputted to each of the two or more through vias having the same potentials.

8. The semiconductor device of claim 6 , wherein the two or more through vias having the same potentials form the same power supply line.

9. The semiconductor device of claim 6 , wherein one of the two or more through vias having the same potentials is disposed at a peripheral portion of the via group.

10. The semiconductor device of claim 1 , wherein at least one of the via groups includes a first through via having a first potential, and a second through via having a second potential complementary to the first potential, and adjacent to the first through via.

11. The semiconductor device of claim 10 , wherein the first through via forms a power supply line, and the second through via forms a ground line.

12. The semiconductor device of claim 10 , wherein

the via group further includes a third through via to which a signal is inputted, and

the first through vias and the second through vias are alternately arranged so as to surround the third through via.

13. The semiconductor device of claim 1 , wherein the via groups are equidistantly arranged.

14. The semiconductor device of claim 1 , wherein at least one of the via groups includes a dummy through via not used for an electrical connection.

15. The semiconductor device of claim 14 , wherein the dummy through via is disposed at a peripheral portion of the via group.

16. The semiconductor device of claim 1 , wherein at least one of the via groups includes an auxiliary through via which assists an electrical connection of another through via.

17. The semiconductor device of claim 16 , wherein the auxiliary through via is disposed at a peripheral portion of the via group.

18. A stacked semiconductor device is a stacked semiconductor device in which a plurality of semiconductor devices are stacked, wherein

at least one of the plurality of semiconductor devices is the semiconductor device of claim 1 .

19. A stacked semiconductor device is a stacked semiconductor device in which a plurality of semiconductor devices are stacked, wherein

each of two or more of the plurality of semiconductor devices is the semiconductor device of claim 1 , and the individual via groups in each of the two or more semiconductor devices are arranged so as not to overlap each other.

20. A stacked semiconductor device is a stacked semiconductor device in which a plurality of semiconductor devices are stacked, wherein

each of two or more of the plurality of semiconductor devices is a semiconductor device having a plurality of through vias extending through a substrate,

the plurality of through vias are arranged dividedly in three or more via groups, and

each of the via groups includes three or more of the through vias that are arranged in two dimensions, and

the individual via groups in each of the two or more semiconductor devices are arranged so as not to overlap each other.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 053570/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2010
From: NISHIO, TAICHI; HIRANO, HIROSHIGE; OTA, YUKITOSHI
To: PANASONIC CORPORATION
Reel/Frame 025214/0159 →