SRAM cell for single sided write
View Patent ↗A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage.
1. An integrated circuit, comprising:
an array of SRAM cells configured in rows and columns, each said SRAM cell including:
a bit driver, said bit driver including a drain node, a source node, and a gate node;
a bit-side node connected to said drain node of said bit driver;
a bit load, said bit load including a drain node connected to said bit-side node, a source node, and a gate node;
a bit-bar driver, said bit-bar driver including a drain node, a source node, and a gate node connected to said bit-side node;
a bit-bar side node connected to said drain node of said bit-bar driver, to said gate node of said bit driver and to said gate node of said bit load, said bit-bar side node being free of a connection to a passgate transistor;
a bit-bar load, said bit-bar load including a drain node connected to said bit-bar side node, a source node, and a gate node connected to said bit-side node;
a bit-side passgate, said bit-side passgate including a first source/drain node connected to said bit-side node, a second source/drain node connected to a bit line, and a gate node connected to a word line;
and a bit-bar-side auxiliary driver transistor, said bit-bar-side auxiliary driver transistor including a drain node directly connected to said bit-bar side node, a source node, and a gate node connected to said bit-side node; and node, a source node, and a gate node connected to said bit-side node; and
an auxiliary driver transistor bias circuit coupled to said source node of said bit-bar-side auxiliary driver transistor in said each said SRAM cell, such that said auxiliary driver transistor bias circuit is capable of biasing said source nodes of said bit-bar-side auxiliary driver transistors in said array of SRAM cells.
2. The integrated circuit of claim 1 , in which said auxiliary driver transistor bias circuit is capable of biasing said source nodes of said bit-bar-side auxiliary driver transistors in addressed SRAM cells of said array of SRAM cells independently of said source nodes of said bit-bar-side auxiliary driver transistors in half-addressed SRAM cells of said array of SRAM cells.
3. The integrated circuit of claim 1 , in which a boost voltage is provided during a single sided write high operation on said word line between 100 and 400 millivolts above a bias voltage on said source nodes of said bit loads and said bit-bar loads.
4. The integrated circuit of claim 1 , in which an intermediate write potential is provided during a single sided write high operation on said word line that is substantially equal to a bias voltage on said source nodes of said bit loads and said bit-bar loads for between 0.5 and 2 nanoseconds, followed by a boost voltage on said word line between 100 and 400 millivolts above said bias voltage on said source nodes of said bit loads and said bit-bar loads.
5. A method comprising:
performing a single skied read operation on an addressed SRAM cell in an SRAM cell array, by a process including:
floating a source node of a bit-bar-side auxiliary driver transistor of a half-addressed SRAM cell in said SRAM cell array;
floating a source node of a bit-bar-side auxiliary driver transistor of said addressed SRAM cell; and
subsequently turning on a bit-side passgate of said addressed SRAM cell and turning on a bit-side passgate of said half-addressed SRAM cell;
Performing a single side write low operation on said addressed SRAM cell by a process including floating said source node of said bit-bar-side auxiliary driver transistor of said half addressed SRAM cell, said bit-bar-side auxiliary driver transistor having a drain node directly connected to a bit-bar side node; and
performing a single sided write high operation on said addressed SRAM cell by a process including floating said source node of said bit-bar-side auxiliary driver transistor of said half-addressed SRAM cell.
6. The method of claim 5 , in which said single sided write high operation includes:
biasing said source node of said bit-bar-side auxiliary driver transistor of said addressed SRAM cell to a low bias voltage; and
turning on said bit-side passgate of said addressed SRAM cell.
7. The method of claim 5 , in which said single sided write low operation includes:
floating said source node of said bit-bar-side auxiliary driver transistor of said addressed SRAM cell; and
turning on said bit-side passgate of said addressed SRAM cell.
8. The method of claim 5 , in which said single sided write low operation includes:
biasing said source node of said bit-bar-side auxiliary driver transistor of said addressed SRAM cell to a high bias voltage; and
turning on said bit-side passgate of said addressed SRAM cell.
9. The method of claim 5 , in which said single sided write high operation includes providing a boost voltage on said word line that is between 100 and 400 millivolts above a bias voltage on source nodes of a bit load and a bit-bar load of said addressed SRAM cell.
10. The method of claim 5 , in which said single sided write high operation includes:
biasing said word line to a potential that is substantially equal to a bias voltage on source nodes of a bit load and a bit-bar load of said addressed SRAM cell for a time that is between 0.5 and 2 nanoseconds; and
providing a boost voltage on said word line that is between 100 and 400 millivolts above a bias voltage on said source nodes of said bit load and said bit-bar load.