Apparatus of memory array using finfets
A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
1. Apparatus, comprising:
a pair of memory elements;
a pair of contact elements, each of the contact elements coupled to one memory element of the pair of memory elements;
a pair of fins, laterally extending in parallel above the surface of a substrate, each fin of the pair of fins partially wrapped by a common source line, and each fin of the pair of fins partially wrapped by one contact element of the pair of contact elements;
a common gate line partially wrapping each of the pair of fins between a source region and a drain region of each of the fins; and
a pair of bit lines extending laterally in parallel to the fins, above, but not in contact with the gate line, each of the bit lines coupled to one memory element of the pair of memory elements.
2. The apparatus of claim 1 , wherein the area of each unit of the memory cell array is a function of a pitch of the pair of fins, a width of the source line, and a width of each contact element of the pair of contact elements.
3. The apparatus of claim 1 , wherein the pitch of the pair of fins is substantially 100 nm.
4. The apparatus of claim 1 wherein the width of the source line is substantially 20 nm.
5. The apparatus of claim 1 , wherein the width of each contact element of the pair of contact elements is substantially 40 nm.
6. The apparatus of claim 1 , wherein each memory element of the pair of memory elements is a NVM.
7. The apparatus of claim 1 , wherein each contact element of the pair of contact elements is made of material selected from one or more of tungsten, copper, silver, gold, aluminum, and their alloys.
8. The apparatus of claim 1 , wherein the source line is made of material selected from one or more of tungsten, copper, silver, gold, and aluminum.
9. The apparatus of claim 1 , wherein each bit line of the pair of bit lines is made of material selected from one or more of tungsten, copper, silver, gold, and aluminum.
10. The apparatus of claim 1 , wherein the gate line is made of poly silicon.
11. The apparatus of claim 1 , wherein the space between the source line, the fin lines, the contact elements, and the gate line is filled with BPSG (borophosphosilicate glass).
12. The apparatus of claim 1 , wherein the space between the source line, the gate line, the bit lines, and the memory elements is filled with SiO 2 (silicon oxide).
13. The apparatus of claim 1 , wherein the source region of each fin of the pair of fins is partially wrapped by the common source line.
14. The apparatus of claim 1 , wherein the drain region of each fin of the pair of fins is partially wrapped by the one contact element of the pair of contact elements.
15. The apparatus of claim 1 , wherein each of the contact elements are vertically oriented.