Semiconductor integrated circuit device and manufacturing method thereof
View Patent ↗After silicon oxide film ( 9 ) is formed on the surface of a semiconductor substrate ( 1 ), the silicon oxide film ( 9 ) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film ( 10 ) is formed on the semiconductor substrate ( 1 ). Consequently, two kinds of gate insulation films, namely, a gate insulation film ( 12 ) comprised of stacked film of high dielectric constant insulation film ( 10 ) and silicon oxide film ( 9 ) and gate insulation film ( 11 ) comprised of the high dielectric constant insulation film ( 10 ) are formed on the semiconductor substrate ( 1 ).
1. A method of manufacturing a semiconductor integrated circuit device having a first MISFET for use as a selecting MISFET of a memory cell formed in a first region of a semiconductor substrate; and a second MISFET formed in a second region of the semiconductor substrate, the method comprising:
(a) forming a first insulating film over the first and second regions;
(b) after the step (a), removing the first insulating film over the second region, wherein the first insulating film over the first region is kept;
(c) after the step (b), forming a second insulating film over the second region;
(d) after the step (c), forming a third insulating film, a first portion of the third insulating film being formed over the first insulating film of the first region and a second portion of the third insulating film being formed over the second insulating film of the second region; and
(e) after the step (d), forming a first gate electrode of the first MISFET over the first portion of the third insulating film and forming a second gate electrode of the second MISFET over the second portion of the third insulating film,
wherein a first gate insulating film of the first MISFET is comprised of the first insulating film and the first portion of the third insulating film,
wherein a second gate insulating film of the second MISFET is comprised of the second insulating film and the second portion of the third insulating film,
wherein the first and second insulation films include silicon, oxygen, and nitrogen,
wherein the first and second portions of the third insulation film of the first and second MISFETs, respectively, have a greater dielectric constant than each of the first and second insulation films,
wherein a thickness of the first insulation film is larger than a thickness of the second insulation film, and
wherein thicknesses of the first and second portions of the third insulation film of the first and second MISFETs, respectively, are larger than the thicknesses of the first insulation film and the second insulation film, respectively.
2. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the first insulation film is made of a silicon oxynitride film.
3. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the second insulation film is made of a silicon oxynitride film.
4. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the third insulation film is made of a hafnium oxide film.
5. a method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the memory cell is a dynamic random access memory cell.
6. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the first MISFET is an n-type MISFET.