Signal processing block for a receiver in wireless communication
View Patent ↗A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented ( 290 ) that uses un-rolled pipelined CORDIC processors ( 245 a to 245 d ) iteratively to improve throughput and resource utilization, while reducing the gate count.
1. A method for transforming a first matrix using a computer comprising a pipelined structure including an input stage, a plurality of Coordinate Rotation Digital Computer (CORDIC) processors, and an output stage, the method comprising:
receiving and storing the first matrix by the input stage;
generating, using the CORDIC processors, a second matrix from the first matrix using a real-value decomposition (RVD), wherein elements of the second matrix comprise real values determined based on either real part or imaginary part of a corresponding element in the first matrix; and
performing, using CORDIC processors, a plurality of Givens rotation operations and at least one multi-dimensional Householder reflection operation on one or more elements of the second matrix to generate a third matrix, wherein each Givens rotation operation annihilates at least one element of the third matrix and each multi-dimensional Householder reflection operation annihilates at least two elements of the third matrix.
2. The method of claim 1 wherein the third matrix is a triangular matrix.
3. The method of claim 1 wherein performing the plurality of Givens rotation operations comprises:
concurrently performing a plurality of two-dimensional Givens rotation operations on a plurality of independent sets of rows of the second matrix.
4. The method of claim 1 wherein performing the multi-dimensional Householder reflection operation comprises:
performing at least one multi-dimensional Householder reflection operation to concurrently annihilate two or more elements of the third matrix that correspond to common pivot rows.
5. The method of claim 1 wherein performing the plurality of Givens rotation operations comprises:
performing at least one four-dimensional Givens rotation to concurrently annihilate three elements of the third matrix.
6. The method of claim 1 wherein the third matrix corresponds to a triangular matrix R in QR decomposition of the first matrix.
7. The method of claim 1 wherein the first matrix represents a channel between a plurality of transmit antennas and a plurality of receive antennas, the method further comprising:
generating a fourth matrix by performing the plurality of Givens rotation operations and the at least one Householder reflection operation on a matrix of received signals.
8. The method of claim 1 wherein the first matrix comprises a plurality of complex value elements.
9. The method of claim 1 , wherein performing the plurality of Givens rotation operations comprises:
performing the plurality of Givens rotations on the one or more elements of the second matrix according to a predefined sequence to maintain symmetry between adjacent columns of one or more intermediate matrices.
10. A processor comprising a pipelined structure including an input stage, a plurality of Coordinate Rotation Digital Computer (CORDIC) processors, and an output stage, the processor being configured to:
receive and store a first matrix by the input stage;
generate, using the CORDIC processors, from the first matrix, a second matrix using a real-value decomposition (RVD), the second matrix comprising real valued elements determined based on either real part or imaginary part of a corresponding element in the first matrix; and
perform, using the CORDIC processors, a plurality of Givens rotation operations and at least one multi-dimensional Householder reflection operation on one or more elements of the second matrix to generate a third matrix, wherein each Givens rotation operation annihilates at least one element of the third matrix and each multi-dimensional Householder reflection operation annihilates at least two elements of the third matrix.
11. The processor of claim 10 wherein the third matrix is a triangular matrix.
12. The processor of claim 10 wherein the processor is further configured to concurrently perform a plurality of two-dimensional Givens rotation operations on a plurality of independent sets of rows of the second matrix.
13. The processor of claim 10 wherein the processor is further configured to perform at least one multi-dimensional Householder reflection operation to concurrently annihilate two or more elements of the third matrix that correspond to common pivot rows.
14. The processor of claim 10 wherein the processor is further configured to perform at least one four-dimensional Givens rotation to concurrently annihilate three elements of the third matrix.
15. The processor of claim 10 wherein the third matrix corresponds to a triangular matrix R in QR decomposition of the first matrix.
16. The processor of claim 10 wherein the first matrix represents a channel between a plurality of transmit antennas and a plurality of receive antennas, and the processor is further configured to generate a fourth matrix by performing the plurality of Givens rotation operations and the at least one Householder reflection operation on a matrix of received signals.
17. The processor of claim 10 wherein the first matrix comprises a plurality of complex value elements.
18. The processor of claim 10 wherein the plurality of Givens rotation operations and the at least one Householder reflection operation are performed using the CORDIC processors.