Method and apparatus to improve dynamic response of the synchronous rectifying for resonant power converters
View Patent ↗A synchronous rectifying circuit for a switching power converter is provided. The synchronous rectifying circuit includes a power transistor, a diode, and a control circuit. The power transistor and the diode are coupled to a transformer and an output of the power converter for rectification. The control circuit generates a drive signal to switch on the power transistor once the diode is forward biased. The control circuit includes a monitor circuit. The monitor circuit generates a monitor signal an off signal to switch off the power transistor in response to a pulse width of the drive signal for generating an off signal to switch off the power transistor. The monitor circuit further reduces the pulse width of the drive signal in response to a change of a feedback signal. The feedback signal is correlated to an output load of the power converter.
1. A synchronous rectifying circuit for a switching power converter comprises:
a power transistor and a diode coupled to a transformer and an output of the power converter for rectification; and a control circuit generating a drive signal to switch on the power transistor once the diode is forward biased, wherein the control circuit comprises:
a monitor circuit generating a monitor signal in response to a pulse width of the drive signal for generating an off signal to switch off the power transistor;
wherein the monitor circuit generates a threshold and further enables the monitor signal when a change of a feedback signal is over the threshold to reduce the pulse width of the drive signal; and wherein the feedback signal is correlated to an output load of the power converter; and wherein the wherein the monitor circuit comprises: a charge circuit generating a ramp signal when the drive signal is enabled; a sample circuit generating a hold signal in accordance with the level of the ramp signal; an amplifier generating a threshold signal in accordance with the level of the hold signal; and
a comparator generating the monitor signal in response to comparison of the ramp signal and the threshold signal; wherein the level of the hold signal is correlated to the level of the feedback signal.
2. The synchronous rectifying circuit as claimed in claim 1 , wherein the control circuit further comprises a detection circuit, wherein the detection circuit comprises:
a charge circuit generating a ramp signal when the drive signal is enabled by an on signal;
a sample circuit generating a hold signal in accordance with the level of the ramp signal; and
a comparator generating the off signal in response to comparison of the ramp signal and the hold signal;
wherein the level of the hold signal is correlated to the pulse width of the on signal.
3. The synchronous rectifying circuit as claimed in claim 2 , wherein the detection circuit further comprises:
a detector generating a restart signal coupled to decrease the level of the hold signal;
wherein the restart signal is generated when the change of the feedback signal is over the threshold.
4. A synchronous rectifying circuit for a switching power converter comprises:
a power transistor and a diode coupled to a transformer and an output of the power converter for rectification; and
a control circuit generating a drive signal to switch on the power transistor once the diode is forward biased, wherein the control circuit comprises:
a debounce circuit generating a debounce signal according to an on signal to switch off the power transistor;
wherein when a turn on period of the on signal is larger than a predetermined period, the debounce circuit turns on the debounce signal to reduce the pulse width of the drive signal; and wherein the debounce circuit comprises:
an inverter receiving the on signal;
a PMOS transistor, wherein a gate of the PMOS transistor receives the on signal through the inverter;
an NMOS transistor, wherein a gate of the NMOS transistor receives the on signal through the inverter; a first current source coupled between a voltage source and a source of the PMOS transistor;
a second current source coupled between a source of the NMOS transistor and a ground; and a capacitor having a first terminal coupled a joint between drains of the PMOS transistor and the NMOS transistor and a second terminal coupled to the ground;
wherein the debounce signal is generated at the joint between the drains of the PMOS transistor and the NMOS transistor.
5. The synchronous rectifying circuit as claimed in claim 4 , wherein the control circuit further comprises a phase detection circuit, wherein the detection circuit comprises:
a charge circuit generating a ramp signal when the drive signal is enabled by the on signal;
a sample circuit generating a hold signal in accordance with the level of the ramp signal; and
a comparator generating an off signal in response to comparison of the ramp signal and the hold signal for switch off the power transistor;
wherein the level of the hold signal is correlated to the pulse width of the on signal.
6. The synchronous rectifying circuit as claimed in claim 5 , wherein the phase detection circuit further comprises:
a detector generating a restart signal coupled to decrease the level of the hold signal; and
wherein the restart signal is generated in response to a shrink signal and a pulse signal.
7. A synchronous rectifying method for a switching power converter, wherein a power transistor and a diode coupled to a transformer and an output of the power converter for rectification, the method comprises:
generating a drive signal to switch on the power transistor once the diode is forward biased;
generating a monitor signal in response to a pulse width of the drive signal for
generating an off signal to switch off the power transistor; generating a threshold; and when a change of a feedback signal is over the threshold, enabling the monitor signal to reduce the pulse width of the drive signal;
wherein the feedback signal is correlated to an output load of the power converter;
wherein the step of generating the monitor signal comprises:
generating a ramp signal when the drive signal is enabled; generating a hold signal in accordance with the level of the ramp signal; generating a threshold signal in accordance with the level of the hold signal; and
generating the monitor signal in response to comparison of the ramp signal and the threshold signal; wherein the level of the hold signal is correlated to the level of the feedback
signal.
8. The method as claimed in claim 7 further comprising:
generating a ramp signal when the drive signal is enabled by an on signal;
generating a hold signal in accordance with the level of the ramp signal; and
generating the off signal in response to comparison of the ramp signal and the hold signal;
wherein the level of the hold signal is correlated to the pulse width of the on signal.
9. The method as claimed in claim 8 further comprising:
generating a restart signal to decrease the level of the hold signal when the change of the feedback signal is over the threshold.