IP Library Patent Application 12787054
Patent Application
App. No. 12/787,054

METHOD AND SYSTEM FOR BANDWIDTH REDUCTION THROUGH INTEGRATION OF MOTION ESTIMATION AND MACROBLOCK ENCODING

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Patent No.
US None
App. No.
12/787,054
Abstract

Video data for a current frame and a plurality of reference frames may be loaded into a video codec in a video processing device from a memory used in the video processing device, and the loaded video data may be buffered in an internal buffer used during motion estimation. Motion estimation may be performed based on the loaded video data, and after completion of the motion estimation, macroblock encoding for the current frame may be performed based on the loaded video data and the motion estimation. The motion estimation may comprise coarse motion estimation and fine motion estimation, and motion vectors may be generated based on the motion estimation on per-macroblock basis. The encoding may comprise macroblock encoding of a residual for the current frame, which may be determined based on the original video data, accessed from the internal motion estimation buffer, and prediction determined based on the generated motion vectors.

Claims (27)

1 . A method for video processing, the method comprising:

in a video processing device that processes a plurality of video frames:

estimating motion associated with a current one of said plurality of video frames utilizing motion estimation based on video data corresponding to said current one of said plurality of video frames and one or more reference frames;

and

macroblock encoding said current one of said plurality of video frames based on said estimated motion, wherein said video data is loaded from a memory once for said motion estimation and said macroblock encoding.

2 . The method according to claim 1 , comprising buffering said video data in an internal buffer used during said motion estimation.

3 . The method according to claim 2 , wherein said internal motion estimation buffer is accessible during said macroblock encoding.

4 . The method according to claim 1 , comprising performing coarse motion estimation and fine motion estimation during said motion estimation.

5 . The method according to claim 1 , comprising generating motion vectors based on said motion estimation.

6 . The method according to claim 1 , wherein said macroblock encoding comprises macroblock encoding a residual of said current one of said plurality of video frames, said residual comprising parts of said current one of said plurality of video frames not predictable based on said motion estimation.

7 . The method according to claim 6 , comprising generating said residual by subtracting predicted motion vectors generated based on said motion estimation from original video data corresponding to said current one of said plurality of video frames.

8 . The method according to claim 1 , comprising performing said motion estimation and/or said macroblock encoding based on H.264/AVC standard.

9 . The method according to claim 8 , wherein said video processing device is operable to perform video encoding and/or decoding based on VC-1, MPEG-1, MPEG-2, MPEG-4 and/or AVS standards.

10 . The method according to claim 8 , wherein said video processing device is operable to perform video encoding and/or decoding based on legacy video compression standards, said legacy video compression standards comprising On2 VP7 and/or H.263 standards.

11 . A system for video processing, the system comprising:

one or more circuits and/or processors in a video processing device that processes a plurality of video frames, said one or more circuits and/or processors are operable to:

estimate motion associated with a current one of said plurality of video frames utilizing motion estimation based on video data corresponding to said current one of said plurality of video frames and one or more reference frames; and

macroblock encode said current one of said plurality of video frames based on said estimated motion, wherein said video data is loaded from a memory once for said motion estimation and said macroblock encoding.

12 . The system according to claim 11 , wherein said one or more circuits and/or processors are operable to buffer said video data in an internal buffer used during said motion estimation.

13 . The system according to claim 12 , wherein said internal motion estimation buffer is accessible during said macroblock encoding.

14 . The system according to claim 11 , wherein said one or more circuits and/or processors are operable to perform coarse motion estimation and fine motion estimation during said motion estimation.

15 . The system according to claim 11 , wherein said one or more circuits and/or processors are operable to generate motion vectors based on said motion estimation.

16 . The system according to claim 11 , wherein said macroblock encoding comprises macroblock encoding a residual of said current one of said plurality of video frames, said residual comprising parts of said current one of said plurality of video frames not predictable based on said motion estimation.

17 . The system according to claim 16 , wherein said one or more circuits and/or processors are operable to generate said residual by subtracting predicted motion vectors generated based on said motion estimation from original video data corresponding to said current one of said plurality of video frames.

18 . The system according to claim 11 , wherein said one or more circuits and/or processors are operable to perform said motion estimation and/or said macroblock encoding based on H.264/AVC standard.

19 . The system according to claim 18 , wherein said video processing device is operable to perform video encoding and/or decoding based on VC-1, MPEG-1, MPEG-2, MPEG-4 and/or AVS standards.

20 . The system according to claim 18 , wherein said video processing device is operable to perform video encoding and/or decoding based on legacy video compression standards, said legacy video compression standards comprising On2 VP7 and/or H.263 standards.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2010
From: DE RIVAZ, PETER FRANCIS CHEVALLEY
To: BROADCOM CORPORATION
Reel/Frame 024726/0242 →