Semiconductor device
Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region. The third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar. The first-conductive type impurity region of each of the second silicon pillar and the third silicon pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type high-concentration impurity region of a respective one of the second silicon pillar and the third silicon pillar.
1. A semiconductor device comprising:
a first-conductive type first silicon pillar on a first-conductive type silicon substrate:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric; and
a third silicon pillar on a top of the first silicon pillar,
wherein:
the silicon substrate has a second-conductive type high-concentration impurity region formed in a part thereof; and
the third silicon pillar including a second-conductive type high-concentration impurity region in a peripheral surface thereof except in at least a central portion of a contact surface region with the first silicon pillar, the central portion characterized by a diameter that is less than a diameter of the third silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity, where the second-conductive type is of an opposite conductivity to the first conductive type and thereby a p-n junction resides at an interface thereof,
and wherein the first-conductive type impurity region has a length that extends from a base portion of the second-conductive type high-concentration impurity region to the contact surface region, and the length is greater than that of a depletion layer extending from the base portion.
2. The semiconductor device as defined in claim 1 , which satisfies the following relation:
Ls
>
Ts
4
,
wherein Ls and Ts are, respectively, a length and a diameter of the first-conductive type impurity region of the third silicon pillar on a source side.
3. The semiconductor device as defined in claim 1 , which satisfies the following relation:
Ld
>
Td
4
,
wherein Ld and Td are, respectively, a length and a diameter of the first-conductive type impurity region of the third silicon pillar on a drain side.
4. The semiconductor device as defined in claim 1 , wherein:
the first silicon pillar is comprises a high resistance region;
the second-conductive type impurity region of the silicon substrate is comprises a high resistance region; and
the first-conductive type impurity region of the third silicon pillar comprises a high resistance region.
5. A semiconductor device comprising:
a first-conductive type first silicon pillar on a first-conductive type silicon substrate:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric; and
a third silicon pillar on a top of the first silicon pillar,
wherein:
the silicon substrate includes a second-conductive type high-concentration impurity region in a part thereof; and
the third silicon pillar includes a second-conductive type high-concentration impurity region in a peripheral surface thereof except in at least a part of a contact surface region with the first silicon pillar, the central portion characterized by a diameter that is less than a diameter of the third silicon pillar, and a first-conductive type impurity region therein and surrounded by the second-conductive type high-concentration impurity region, where the second-conductive type is of an opposite conductivity to the first conductive type and thereby a p-n junction resides at an interface thereof,
and wherein the first-conductive type impurity region has a length that extends from a base portion of the second-conductive type high-concentration impurity region to the contact surface region, which is short enough to allow the second-conductive type high-concentration impurity region of the third silicon pillar to be formed.
6. The semiconductor device as defined in claim 5 , wherein:
the first silicon pillar comprise a high resistance region;
the second-conductive type impurity region of the silicon substrate comprises a high resistance region; and
the first-conductive type impurity region of the third silicon pillar comprises a high resistance region.
7. A semiconductor device comprising:
a first-conductive type first silicon pillar formed on a first-conductive type silicon substrate:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric; and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the silicon substrate has a second-conductive type high-concentration impurity region formed in a part thereof; and
the third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein the first-conductive type impurity region of the third silicon pillar has a length which is short enough to allow the second-conductive type high-concentration impurity region of the third silicon pillar to be formed and which satisfies the following relation:
tan
(
π
36
)
·
Tspace
-
Ljs
>
Ls
,
wherein: Tspace is a distance between adjacent two of a plurality of the semiconductor devices formed on the silicon substrate;
Ljs is a depth of the second-conductive type high-concentration impurity region formed in the third silicon pillar to serve as a source; and
Ls is a length of the first-conductive type impurity region of the third silicon pillar.
8. A semiconductor device comprising:
a first-conductive type first silicon pillar formed on a first-conductive type silicon substrate:
a first dielectric surrounding a side surface of the first silicon pillar;
a gate surrounding the dielectric; and
a third silicon pillar provided on a top of the first silicon pillar,
wherein:
the silicon substrate has a second-conductive type high-concentration impurity region formed in a part thereof; and
the third silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region of the third silicon pillar,
and wherein the first-conductive type impurity region of the third silicon pillar has a length which is short enough to allow the second-conductive type high-concentration impurity region of the third silicon pillar to be formed and which satisfies the following relation:
tan
(
π
36
)
·
Tspace
-
Ljd
>
Ld
,
wherein: Tspace is a distance between adjacent two of a plurality of the semiconductor devices formed on the silicon substrate;
Ljd is a depth of the second-conductive type high-concentration impurity region formed in the third silicon pillar to serve as a drain; and
Ld is a length of the first-conductive type impurity region of the third silicon pillar.