Input pin state detection circuit and method therefor
A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.
1. An input state detection circuit comprising:
an input pin configured for receiving signals generated by a plurality of different types of input circuits;
a state-detection circuit configured to provide an output characterizing the state of the input pin for a plurality of input states respectively corresponding to the plurality of different types of input circuits, the state-detection circuit having
a plurality of comparators respectively having their high-level inputs directly coupled to the input pin, having their low-level inputs coupled between a power source and a ground node, and configured to provide a binary output that, when collectively processed with the binary outputs of the other comparators, indicates the state of the input pin,
a resistor circuit connected in series between a first one of the comparators and the power source,
for each pair of comparators having input pins connected in series, a resistor circuit connected therebetween,
a resistor circuit connected between a last one of the comparators and the ground node;
a negative-feedback operational amplifier having an output connected to the high-level input of the comparators, having a high-level input, a low-level input and a feedback circuit connecting the output to the low-level input;
a resistor circuit connected between the high-level input of the negative-feedback operational amplifier and a feedback power source; and
a resistor circuit connected between the high-level input of the negative-feedback operational amplifier and a feedback ground node.
2. The circuit of claim 1 , further including a decoder circuit coupled to the outputs of the comparators and configured to detect the state of the input pin based upon the binary outputs of the comparators and to provide the detected state for operating an integrated circuit connected to the input pin.
3. The circuit of claim 1 , further including a control circuit configured to
power on the state-detection circuit for an initialization cycle during which the state of the input pin is detected, and
after the state of the input pin has been detected, power off the state-detection circuit and use the detected state to operate an integrated circuit connected to the input pin.
4. The circuit of claim 1 , further including a control circuit configured to,
during an initialization period, power on the state-detection circuit and detect the state of the input pin based upon the binary outputs of the comparators, and
after the initialization period, power off the state-detection circuit and provide the detected state for operating an integrated circuit connected to the input pin.
5. The circuit of claim 1 , further including a control circuit configured to,
during an initialization period, power on the state-detection circuit and detect the state of the input pin based upon the binary outputs of the comparators,
after the initialization period, power off the state-detection circuit and provide the detected state for operating an integrated circuit connected to the input pin,
after operating the integrated circuit, in response to a reset event, re-power the state-detection circuit and re-detect the state of the input pin based upon the binary outputs of the comparators, and
after re-detecting the state of the input pin, power off the state-detection circuit and provide the re-detected state for operating the integrated circuit.
6. The circuit of claim 1 , wherein the state-detection circuit is configured to provide a plurality of binary output values, via the comparators, to indicate states of the input pin corresponding to input circuits that respectively couple the input pin to ground via a short, to ground via a resistor, to an open circuit, to a reference voltage via a resistor, and to a reference voltage via a short.
7. The circuit of claim 1 , wherein the state-detection circuit is configured to provide different binary output values based upon the presence of a resistor coupled between the input pin and at least one of a source and ground.
8. The circuit of claim 1 , further including another of the state-detection circuits connected to a second input pin, the respective state detection circuits being configured to provide respective binary output values that, when combined, provide a number of states of the input pin that is a multiple of the number of individual binary outputs for each circuit.
9. The circuit of claim 1 , wherein the respective resistor circuits coupled to the inputs of the comparators have a common resistance.
10. A configurable input circuit for operating in accordance with a plurality of different input circuits, the input circuit comprising:
an input pin to receive an input signal;
a state-detection circuit configured to, upon start-up of the configurable input circuit, provide a binary output signal for determining a state characteristic of the input signal, the state detection circuit having an output that provides at least N−1 output values that make up the binary output signal, the output signal being responsive to the state of the input pin and exclusive for each of N different types of input circuits, wherein N is an integer greater than two;
a decoder circuit configured to decode the binary output to determine the state of the input pin and a type of input circuit corresponding to the determined state; and
a control circuit configured to power-on the state-detection circuit upon startup of the configurable input circuit, to power-off the state-detection circuit in response to the decoder circuit determining the state of the input signal, and to configure the input circuit for operation based upon the determined state of the input pin.
11. The circuit of claim 10 , wherein the state-detection circuit includes a resistor tree divider circuit having output nodes between the respective resistors, the output nodes respectively providing resistance-based voltage values for use by the state-detection circuit in determining the state characteristic.
12. The circuit of claim 10 , wherein the state-detection circuit includes
a resistor tree divider circuit having output nodes between the respective resistors coupled between a reference voltage and ground, the output nodes respectively providing resistance-based voltage values for use by the state-detection circuit in determining the state characteristic, and
at least one comparator connected to the input pin and an output node of the resistor tree divider circuit, the comparator being configured to compare the input signal provided via the input pin with a value at an output node and to provide a compared output value that forms part of the binary output signal.
13. The circuit of claim 10 , wherein the state-detection circuit includes
a resistor tree divider circuit having output nodes between the respective resistors coupled between a reference voltage and ground, the output nodes respectively providing resistance-based voltage values for use by the state-detection circuit in determining the state characteristic,
a switch circuit connected to at least two of the output nodes and configured to provide a switched output corresponding to one of the at least two output nodes, and
for each switched output, a comparator connected to the switched output and configured to compare the input signal provided via the input pin with a value at the switched output and to provide a compared output value that forms part of the binary output signal.
14. The circuit of claim 10 , further comprising at least one additional input pin configured to receive a different input signal, the state-detection circuit being configured to provide the output signal in response to the state of the input pins.
15. The circuit of claim 10 , wherein the state-detection circuit is configured to provide different output values that are dependent upon the presence of a resistor coupled between the input pin and at least one of a source and ground.
16. A method for operating an input circuit, the method comprising:
receiving an input signal at an input pin;
in response to a startup condition, powering a state-detection circuit to provide a binary output signal for determining a state characteristic of the input signal, the state detection circuit providing an output having at least N−1 output values that make up the binary output signal, the output signal being responsive to the state of the input pin and exclusive for each of N different types of input circuits;
in a decoder circuit, decoding the binary output to determine the state of the input pin and a type of input circuit corresponding to the determined state; and
in response to determining the state of the input signal, power-off the state-detection circuit.
17. The method of claim 16 , further including configuring the input circuit for operation based upon the determined state of the input pin.
18. The method of claim 16 ,
further including using a resistor tree divider circuit having output nodes between the respective resistors to provide resistance-based voltage values, and
in the state-detection circuit, comparing the provided resistance-based voltage values to the signal at the input pin to determine the state of the input pin.
19. The method of claim 16 ,
further including using a resistor tree divider circuit having output nodes between the respective resistors to provide resistance-based voltage values, and
selectively providing values of the output nodes to a comparator circuit, and
in the comparator circuit, respectively comparing the input signal to the provided value from each of the output nodes and providing an output for each comparison to form the binary output.
20. The method of claim 16 ,
further comprising receiving an input signal at an additional input pin, and
wherein providing an output having at least N−1 output values that make up the binary output signal includes providing output values for each input pin that combine to set an output signal that is exclusive for each of N×N different types of input circuits.