IP Library Granted Patent US 8,723,489
Granted Patent B2
US 8,723,489 · App. 12/790,783 · Granted May 13, 2014

Bi-directional buck-boost circuit

Inventors: Gopalakrishnan R. Parakulam (Cupertino, CA); Binod Kumar Agrawal (Gurgaon, IN); Saroj Kumar Sahu (Mountain House, CA)
Assignee: Deeya Energy, Inc.
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Quick Facts
Patent No.
US 8,723,489
App. No.
12/790,783
Granted
May 13, 2014
Kind
B2
Abstract

In accordance with some embodiments, a buck-boost circuit is contemplated which is bi-directional. That is, the buck-boost circuit be configured to produce a load voltage for a load responsive to a source voltage from a voltage source, and the buck-boost circuit may also be configured to produce a charging voltage for the voltage source responsive to a second voltage source connected to the load. In an embodiment, the buck-boost circuit may be operating in boost mode when providing the load voltage and may be operating in buck mode when providing the charging voltage.

Claims (51)

1. A buck-boost circuit comprising:

a first voltage bus;

a second voltage bus;

at least one buck-boost converter coupled between the first voltage bus and the second voltage bus;

wherein:

the buck-boost converter is configured to generate a voltage on the first voltage bus responsive to a voltage on the second voltage bus in a first mode of operation during use;

the buck-boost converter is configured to generate the voltage on the second voltage bus responsive to the voltage on the first voltage bus in a second mode of operation during use;

the first mode of operation is a boost mode;

the second mode of operation is a buck mode; and

the buck-boost converter comprises:

an inductor;

a first node;

a first switch in parallel with a first power diode between the second voltage bus and the first node, wherein the first switch is configured to be closed in the buck mode and the first power diode is distinct from the first switch; and

a second switch in parallel with a second power diode between the first node and ground, wherein the second switch is configured to be closed in the boost mode and the second power diode is distinct from the second switch; and

a monitoring circuit configured to:

monitor a voltage across the inductor; and

detect a failure of the buck-boost converter, wherein the failure of the buck-boost converter is indicated when a peak voltage across the inductor is zero.

2. The buck-boost circuit as recited in claim 1 further comprising a buck controller configured to generate a first control signal to the first switch, wherein the first switch is configured to be open or closed responsive to the first control signal.

3. The buck-boost circuit as recited in claim 2 wherein the buck controller is coupled to receive a feedback voltage generated by a feedback circuit responsive to the voltage on the second voltage bus during use, and wherein the feedback circuit is coupled to receive an adjustable control signal and is configured to modify the feedback voltage responsive to the control signal.

4. The buck-boost circuit as recited in claim 3 wherein the buck controller is configured to change a magnitude of the voltage on the second voltage bus responsive to the feedback voltage, and wherein the modification of the feedback voltage causes the buck controller to modify the voltage on the second voltage bus during use.

5. The buck-boost circuit as recited in claim 1 wherein the monitoring circuit is further configured to generate a failure signal to indicate the failure in response to the peak voltage of zero.

6. The buck-boost circuit as recited in claim 1 further comprising a current limiter circuit configured to limit a current to the buck-boost converter to a defined maximum value.

7. The buck-boost circuit as recited in claim 6 wherein the current limiter circuit is configured to latch off if the current to the buck-boost converter reaches the limit, and wherein the current limiter circuit is coupled to receive a latch release signal configured to cause the current limiter circuit to enable from being latched off, and wherein the monitoring circuit is configured to generate the latch release signal.

8. The buck-boost circuit as recited in claim 1 , further comprising a surge current circuit coupled in parallel with the buck-boost converter, wherein the surge current circuit is configured to supply current during a power on event on one of the first voltage bus and the second voltage bus during use, wherein the surge current circuit comprises at least one polyfuse.

9. The buck-boost circuit as recited in claim 8 wherein the at least one polyfuse increases in temperature when supplying the surge current during use, and wherein the polyfuse is configured to create an open circuit in response to reaching a predetermined temperature during use.

10. The buck-boost circuit as recited in claim 1 wherein the first power diode is a power Schottky rectifier and the second power diode is a power Schottky rectifier.

11. A buck-boost circuit comprising:

a first voltage bus;

a second voltage bus;

at least one buck-boost converter coupled between the first voltage bus and the second voltage bus; and

a surge current circuit coupled in parallel with the buck-boost converter;

wherein:

the buck-boost converter is configured to generate a voltage on the first voltage bus responsive to a voltage on the second voltage bus in a first mode of operation during use;

the buck-boost converter is configured to generate the voltage on the second voltage bus responsive to the voltage on the first voltage bus in a second mode of operation during use;

the first mode of operation is a boost mode;

the second mode of operation is a buck mode;

the surge current circuit is configured to supply current during a power on event on one of the first voltage bus and the second voltage bus during use;

the surge current circuit comprises at least one polyfuse; and

the buck-boost converter comprises:

a first node;

a first switch in parallel with a first power diode between the second voltage bus and the first node, wherein the first switch is configured to be closed in the buck mode and the first power diode is distinct from the first switch; and

a second switch in parallel with a second power diode between the first node and ground, wherein the second switch is configured to be closed in the boost mode and the second power diode is distinct from the second switch.

12. The buck-boost circuit as recited in claim 11 further comprising a buck controller configured to generate a first control signal to the first switch, wherein the first switch is configured to be open or closed responsive to the first control signal.

13. The buck-boost circuit as recited in claim 12 wherein the buck controller is coupled to receive a feedback voltage generated by a feedback circuit responsive to the voltage on the second voltage bus during use, and wherein the feedback circuit is coupled to receive an adjustable control signal and is configured to modify the feedback voltage responsive to the control signal.

14. The buck-boost circuit as recited in claim 13 wherein the buck controller is configured to change a magnitude of the voltage on the second voltage bus responsive to the feedback voltage, and wherein the modification of the feedback voltage causes the buck controller to modify the voltage on the second voltage bus during use.

15. The buck boost circuit as recited in claim 11 , further comprising a monitoring circuit configured to detect a failure of the buck-boost converter.

16. The buck-boost circuit as recited in claim 15 wherein the buck-boost converter further comprises an inductor, and wherein the monitoring circuit is configured to monitor a voltage across the inductor.

17. The buck-boost circuit as recited in claim 11 further comprising a current limiter circuit configured to limit a current to the buck-boost converter to a defined maximum value.

18. The buck-boost circuit as recited in claim 17 wherein the current limiter circuit is configured to latch off if the current to the buck-boost converter reaches the limit, and wherein the current limiter circuit is coupled to receive a latch release signal configured to cause the current limiter circuit to enable from being latched off, and wherein the monitoring circuit is configured to generate the latch release signal.

19. The buck-boost circuit as recited in claim 11 wherein the at least one polyfuse increases in temperature when supplying the surge current during use, and wherein the polyfuse is configured to create an open circuit in response to reaching a predetermined temperature during use.

20. The buck-boost circuit as recited in claim 1 wherein the first power diode is a power Schottky rectifier and the second power diode is a power Schottky rectifier.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NO. 8551299 PREVIOUSLY RECORDED AT REEL: 034172 FRAME: 0948. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Jun 10, 2016
From: SILICON VALLEY BANK
To: IMERGY POWER SYSTEMS, INC. (FORMERLY KNOWN AS DEEYA ENERGY, INC.)
Reel/Frame 038950/0114 →
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2014
From: SILICON VALLEY BANK
To: IMERGY POWER SYSTEMS, INC. (FORMERLY KNOWN AS DEEYA ENERGY, INC.)
Reel/Frame 034172/0948 →
CHANGE OF NAME Recorded Oct 7, 2014
From: DEEYA ENERGY, INC.
To: IMERGY POWER SYSTEMS, INC.
Reel/Frame 033908/0957 →
SECURITY INTEREST Recorded Jul 19, 2013
From: DEEYA ENERGY, INC.
To: SILLICON VALLEY BANK
Reel/Frame 030871/0539 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2012
From: SILICON VALLEY BANK
To: DEEYA ENERGY, INC.
Reel/Frame 028314/0741 →
RELEASE OF SECURITY INTEREST Recorded Nov 21, 2011
From: TRIPLEPOINT CAPITAL LLC
To: DEEYA ENERGY, INC.
Reel/Frame 027260/0730 →
SECURITY AGREEMENT Recorded Nov 18, 2011
From: DEEYA ENERGY, INC.
To: SILICON VALLEY BANK
Reel/Frame 027256/0148 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2010
From: PARAKULAM, GOPALAKRISHNAN R.; AGRAWAL, BINOD KUMAR; SAHU, SAROJ KUMAR
To: DEEYA ENERGY, INC.
Reel/Frame 025531/0130 →
SECURITY AGREEMENT Recorded Aug 24, 2010
From: DEEYA ENERGY, INC.
To: TRIPLEPOINT CAPITAL LLC (AS GRANTEE)
Reel/Frame 024880/0804 →
Continuity (2)
Provisional Application 61182082 · May 28, 2009
Related Publication 20110080143A1 · Apr 7, 2011