Integration of processor and input/output hub
Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
1. An integrated circuit device comprising:
a processor; and
an Integrated Input/Output (IIO) logic, at least a portion of which is in hardware, wherein the IIO logic is to provide support for communication between the processor and one or more input/output devices,
wherein a side band signal, to be generated by the IIO logic, is to cause a change in a power management state of the processor and wherein the processor is to comprise sideband control logic to generate a signal to cause a change in a power management state of the IIO logic.
2. The device of claim 1 , wherein the IIO logic is to comprise sideband control logic to generate a signal to indicate the IIO is awake.
3. The device of claim 1 , wherein the processor is to comprise sideband control logic to generate a signal to indicate that the processor is awake.
4. An integrated circuit device comprising:
a processor; and
an Integrated Input/Output (IIO) logic, at least a portion of which is in hardware, wherein the IIO logic is to provide support for communication between the processor and one or more input/output devices,
wherein a side band signal, to be generated by the IIO logic, is to cause a change in a power management state of the processor and wherein the processor is to request the IIO logic to turn on or to turn off.
5. The device of claim 4 , wherein the IIO logic is to generate a signal to indicate power is sufficient within the IIO logic and that the request is asserted.
6. The device of claim 1 , further comprising a first First-In, First-Out (FIFO) device to store data transmitted from the processor to the IIO logic and a second FIFO to store data transmitted to the processor from the IIO logic.
7. The device of claim 1 , further comprising one or more fuses to indicate one or more options associated with the IIO logic.
8. The device of claim 1 , further comprising single frequency selection logic to cause frequency selection for at least one the processor or the IIO logic.
9. The device of claim 1 , wherein the processor is to comprise one or more processor cores.
10. An integrated circuit device comprising:
a processor; and
an Integrated Input/Output (IIO) logic, at least a portion of which is in hardware, wherein the IIO logic is to provide support for communication between the processor and one or more input/output devices,
wherein a side band signal, to be generated by the processor, is to cause a change in a power management state of the IIO logic and wherein the processor is to comprise a sideband control logic to generate a signal, in response to a Platform Environmental Control Interface (PECI) request, to cause power ramp up in the IIO logic.
11. The device of claim 10 , wherein the processor is to comprise sideband control logic to generate the side band signal.
12. The device of claim 10 , wherein the IIO logic is to comprise a sideband control logic to generate a signal to indicate the IIO is awake.
13. The device of claim 10 , wherein the IIO logic is to comprise a sideband control logic to generate a signal to cause a change in a power management state the processor.
14. The device of claim 10 , wherein the IIO logic is to communicate data between a system memory and one or more I/O devices.
15. A method comprising:
generating a first signal, at a first hardware circuitry, to cause a change in a power management state of a processor or an IIO logic, wherein the processor and the IIO logic are on a same integrated circuit die wherein the IIO logic is to provide support for communication between the processor and one or more input/output devices;
generating a second signal, at a second hardware circuitry, in response to the first signal, to indicate that one of the processor or the IIO logic is awake; and
causing, by a single frequency selection logic, frequency selection for the processor and the IIO logic.
16. The method of claim 15 , further comprising communicating data between a system memory and one or more I/O devices via the IIO logic.
17. The method of claim 15 , further comprising storing data transmitted from the processor to the IIO logic in a first FIFO and data transmitted to the processor from the IIO logic in a second FIFO.
18. The device of claim 1 , wherein the processor is to request the IIO logic to turn on or to turn off.
19. The device of claim 4 , wherein the IIO logic is to comprise sideband control logic to generate a signal to indicate the IIO is awake.
20. The device of claim 4 , wherein the processor is to comprise sideband control logic to generate a signal to indicate that the processor is awake.