Method and system for estimating and applying a step size value for LMS echo cancellers
View Patent ↗Disclosed is an improved method and apparatus for estimating and applying a step size value for a least mean squares echo canceller. A power estimate of an excitation signal is compared to a reference power level to determine a shift adjustment. The shift adjustment is added to a reference shift amount to determine a shift amount. The product of an excitation signal and an error signal is then calculated and the product is stored in a memory register comprising a plurality of bits. The bits stored in the memory register are shifted either left or right based upon the shift amount. The shift adjustment may be based in part upon the ratio of the excitation signal power estimate and the reference power level.
1. A method, comprising:
receiving a first excitation signal vector, comprising a plurality of elements, at an echo canceller device comprising a processor and a memory;
determining a power estimate based on an average of one or more absolute values of a plurality of second excitation signal vectors and an absolute value of the first excitation signal vector;
determining a power of two by which the power estimate multiplied by the power of two exceeds a reference power level;
selecting an element from the plurality of elements of the first excitation signal vector;
storing a product of the selected element and a scalar value as a plurality of bits in the memory;
shifting the plurality of bits by a number of bit-shifts, wherein the number of bit-shifts corresponds to the power of two; and
determining an echo cancellation filter coefficient corresponding to the selected element based on the shifted plurality of bits.
2. The method of claim 1 , wherein determining the power estimate based on the average of the one or more absolute values of the plurality of second excitation signal vectors and the absolute value of the first excitation signal vector comprises:
determining a subtracted running average by subtracting a portion of the average of the one or more absolute values of the plurality of second excitation signal vectors from a running average, wherein the running average equals the average of the one or more absolute values of the plurality of second excitation signal vectors; and
adding an equivalent portion of the absolute value of the first excitation signal vector to the subtracted running average.
3. The method of claim 1 , wherein the method further comprises:
updating a filter of the echo canceller device based on the determined echo cancellation filter coefficient.
4. The method of claim 3 , wherein the filter of the echo canceller device comprises a plurality of filter taps, wherein the selected element corresponds to a selected filter tap of the plurality of filter taps, and wherein updating the filter comprises updating a coefficient of the selected filter tap based on the determined echo cancellation filter coefficient.
5. The method of claim 1 , wherein shifting the plurality of bits by the number of bit-shifts comprises determining the number of bit-shifts based on a reference-shift value.
6. The method of claim 5 , wherein determining the number of bit-shifts based on the reference-shift value comprises determining the number of bit-shifts by adding the reference-shift value to a multiple of the power of two.
7. The method of claim 1 , wherein determining the power of two comprises use of a most-significant bit detection (MSBD) opcode.
8. The method of claim 1 , wherein determining the power of two comprises:
setting the power of two to zero;
multiplying the power estimate by two;
comparing the multiplied power estimate to the reference power level; and
responsive to the multiplied power estimate of the excitation signal being less than the reference power level, incrementing the power of two by one.
9. The method of claim 8 , wherein multiplying the power estimate of the excitation signal by two comprises left-shifting bits of the power estimate.
10. A device, comprising:
a memory; and
a processor configured to:
receive a first excitation signal vector comprising a plurality of elements;
determine a power estimate based on an average of one or more absolute values of a plurality of second excitation signal vectors and an absolute value of the first excitation signal vector;
determine a power of two by which the power estimate multiplied by the power of two exceeds a reference power level;
for each element of the plurality of elements of the first excitation signal vector:
storing a product of the element and a scalar value as a plurality of bits in the memory,
shifting the plurality of bits by a number of bit-shifts, wherein the number of bit-shifts corresponds to the power of two, and
determining an echo cancellation filter coefficient corresponding to the element based on the shifted plurality of bits.
11. The device of claim 10 , wherein determining the power estimate based on the average of the one or more absolute values of the plurality of second excitation signal vectors and the absolute value of the first excitation signal vector comprises:
determining a subtracted running average by subtracting a portion of the average of the one or more absolute values of the plurality of second excitation signal vectors from a running average, wherein the running average equals the average of the one or more absolute values of the plurality of second excitation signal vectors; and
adding an equivalent portion of the absolute value of the first excitation signal vector to the subtracted running average.
12. The device of claim 10 , further comprising a filter; and
wherein the processor is further configured to update the filter based on the determined echo cancellation filter coefficient.
13. The device of claim 12 , wherein the filter comprises a plurality of filter taps, and wherein updating the filter comprises updating a coefficient of a filter tap of the plurality of filter taps based on the determined echo cancellation filter coefficient.
14. The device of claim 10 , wherein shifting the plurality of bits by the number of bit-shifts comprises determining the number of bit-shifts based on a reference-shift value.
15. The device of claim 14 , wherein determining the number of bit-shifts based on the reference-shift value comprises determining the number of bit-shifts by adding the reference-shift value to a multiple of the power of two.
16. The device of claim 10 , wherein determining the power of two comprises use of a most-significant bit detection (MSBD) opcode.
17. The device of claim 10 , wherein determining the power of two comprises:
setting the power of two to zero;
multiplying the power estimate by two;
comparing the multiplied power estimate to the reference power level; and
responsive to the multiplied power estimate of the excitation signal being less than the reference power level, incrementing the power of two by one.
18. The device of claim 17 , wherein multiplying the power estimate of the excitation signal by two comprises left-shifting bits of the power estimate.
19. An article of manufacture including a computer-readable storage medium having instructions stored thereon that, in response to execution by a processor, cause the processor to perform operations comprising:
receiving a first excitation signal vector, comprising a plurality of elements, at an echo canceller device comprising a processor and a memory;
determining a power estimate based on an average of one or more absolute values of a plurality of second excitation signal vectors and an absolute value of the first excitation signal vector;
determining a power of two by which the power estimate multiplied by the power of two exceeds a reference power level;
selecting an element from the plurality of elements of the first excitation signal vector;
storing a product of the selected element and a scalar value as a plurality of bits in the memory;
shifting the plurality of bits by a number of bit-shifts, wherein the number of bit-shifts corresponds to the power of two; and
determining an echo cancellation filter coefficient corresponding to the selected element based on the shifted plurality of bits.
20. The article of manufacture of claim 19 , wherein shifting the plurality of bits by the number of bit-shifts comprises determining the number of bit-shifts based on a reference-shift value.