Method for fabrication of a semiconductor device and structure
View Patent ↗A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.
1. A semiconductor device comprising:
a first single crystal silicon layer comprising a plurality of first transistors and a plurality of first alignment marks;
at least two metal layers overlying said first single crystal silicon layer,
wherein said metal layers comprise copper or aluminum more than other materials,
wherein said metal layers provide connections between said first transistors, wherein said metal layers comprise a third metal layer overlying a second metal layer that overlies a first metal layer, and wherein said third metal layer and said first metal layer each has an associated pitch that is tighter than a pitch associated with said second metal layer; and a second thin single crystal silicon layer of less than 0.4 micron thickness overlying said metal layers, wherein said second thin single crystal silicon layer comprises a plurality of second planar transistors, wherein said second planar transistors are aligned with said first alignment marks.
2. A semiconductor device according to claim 1 , wherein said second thin single crystal silicon layer is constructed by a layer transfer process.
3. A semiconductor device according to claim 1 , wherein said plurality of second planar transistors are annealed by an optical annealing.
4. A semiconductor device according to claim 1 , wherein said second planar transistors are source extension transistors.
5. A semiconductor device comprising: a first single crystal silicon layer comprising a plurality of first transistors and a plurality of first alignment marks; at least two metal layers overlying said first single crystal silicon layer, wherein said metal layers comprise copper or aluminum more than other materials, wherein said metal layers provide connections between said first transistors; and a second thin single crystal silicon layer of less than 0.4 micron thickness overlying said metal layers, wherein said second thin single crystal silicon layer comprises a plurality of second planar transistors, wherein said second thin single crystal silicon layer further comprises a second alignment mark, and wherein said plurality of second planar transistors are aligned with said first alignment marks by an offset, wherein said offset relates to a distance between one of said first alignment marks and said second alignment mark.
6. A semiconductor device according to claim 5 , wherein said second thin single crystal silicon layer is constructed by a layer transfer process.
7. A semiconductor device according to claim 5 , wherein said plurality of second planar transistors are annealed by an optical annealing.
8. A semiconductor device according to claim 5 , wherein said second planar transistors are source extension transistors.