IP Library Granted Patent US 9,620,177
Granted Patent B2
US 9,620,177 · App. 12/793,033 · Granted Apr 11, 2017

Internal power supply circuit, semiconductor device, and semiconductor device manufacturing method

Inventor: Koichiro Hayashi (Tokyo, JP)
Assignee: Longitude Semiconductor S.a.r.l.
G11C5/145
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Quick Facts
Patent No.
US 9,620,177
App. No.
12/793,033
Granted
Apr 11, 2017
Kind
B2
Abstract

An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit.

Claims (20)

1. A semiconductor device comprising:

a reference potential generating circuit generating a plurality of reference potentials in parallel to each other, the reference potentials being different in temperature dependency from each other;

a control circuit that selects one of the reference potentials;

an internal voltage generating circuit that generates a power supply voltage with reference to the one of the reference potentials; and

an internal circuit that is supplied with the power supply voltage, wherein

the reference potential generating circuit includes a voltage generating circuit that generates a first voltage having a temperature dependency and second and third voltages having no temperature dependency, and is configured to be capable of selecting a voltage value of the second voltage, a voltage value of the third voltage, a change coefficient to be multiplied by a fourth voltage that is obtained by subtracting the second voltage from the first voltage, and a sign of a fifth voltage that is obtained by multiplying the change coefficient by the fourth voltage, and

the reference potential is generated by adding the third voltage to the fifth voltage.

2. The semiconductor device as claimed in claim 1 , wherein the reference potentials include a first reference potential that rises in accordance with increase of a temperature and a second reference potential that falls in accordance with increasing of the temperature.

3. The semiconductor device as claimed in claim 1 , wherein the reference potentials include first and second potentials rising in accordance with increasing of a temperature, and being different in potential rising rate from each other.

4. The semiconductor device as claimed in claim 1 , wherein the reference potentials being equal to each other at a predetermined temperature.

5. The semiconductor device as claimed in claim 1 , wherein the control circuit selects the reference potential based on information stored in a storing circuit that stores therein the information indicating the reference potential to be generated by the reference potential generating circuit.

6. The semiconductor device as claimed in claim 1 , wherein the control circuit selects the reference potential based on a test code signal that is supplied from outside.

7. A semiconductor device comprising:

a reference potential generating circuit including first and second terminals, the reference potential generating circuit being configured to generate first and second reference potentials such that the first reference potential goes up and the second reference potential goes down in accordance with a temperature increase of the semiconductor device, the reference potential generating circuit being configured to supply the first and second reference potentials respectively to the first and second terminals;

a control circuit coupled to the first and second terminals of the reference potential generating circuit to be supplied with the first and second reference potentials, the control circuit including a third terminal and being configured to supply the third terminal with one of the first and second reference potentials;

an internal voltage generating circuit coupled to the third terminal to be supplied with the one of the first and second reference potentials, and the internal voltage generating circuit being configured to generate a power supply voltage with reference to the one of the first and second reference potentials; and

an internal circuit supplied with the power supply voltage.

8. The semiconductor device as claimed in claim 7 , wherein the reference potential generating circuit is configured to generate the first and second reference potentials such that the first potential is going down and the second potential is going up in accordance with decrease of the temperature of the semiconductor device.

9. The semiconductor device as claimed in claim 8 , wherein the first and second reference potentials become equal to each other when the temperature of the semiconductor device takes a predetermined degree.

10. The semiconductor device as claimed in claim 7 , the control circuit includes a first switching circuit coupled between the first and third terminals and a second switching circuit coupled between the second and third terminals, the control circuit being configured to turn on one of the first and second switch circuit and turn off the other of the first and second switch circuit to supply the third terminal with the one of the first and second potentials.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2021
From: LONGITUDE LICENSING LIMITED
To: NVIDIA CORPORATION
Reel/Frame 057182/0283 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046865/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032898/0001 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2010
From: HAYASHI, KOICHIRO
To: ELPIDA MEMORY, INC.
Reel/Frame 024517/0328 →
Priority Claims (1)
JP 2009-133732 · Jun 3, 2009 · national
Continuity (1)
Related Publication 20100309735A1 · Dec 9, 2010