Semiconductor device

1. A semiconductor device comprising a semiconductor chip in the form of a rectangle having a pair of short sides and a pair of long sides: wherein

the semiconductor chip includes:

(a) a plurality of first bump electrodes arranged along a first long side of the semiconductor chip and arranged at a position closer to the first long side than to a second long side in opposition to the first long side;

(b) an internal circuit formed in the semiconductor chip; and

(c) a plurality of first electrostatic protection circuits which protect the internal circuit against static electricity and are electrically coupled to the first bump electrodes; wherein

a first part of the first electrostatic protection circuits are arranged at a position that overlaps the first bump electrodes to which said first part of the first electrostatic protection circuits are electrically coupled, in a planar view;

a remaining part of the first electrostatic protection circuits are arranged at a position different from a position that overlaps the first bump electrodes to which said remaining part of the first electrostatic protection circuits are electrically coupled, in a planar view;

the remaining part of the first electrostatic protection circuits are all entirely inward of the first part of the first electrostatic protection circuits, in a direction towards the second long side.

2. The semiconductor device according to claim 1 , wherein

the first bump electrodes and the internal circuit are electrically coupled via the first electrostatic protection circuits.

3. The semiconductor device according to claim 1 , wherein

a number of the first bump electrodes which are electrically coupled to the first part the first electrostatic protection circuits is smaller than that of the first bump electrodes which are connected to the remaining part of the first electrostatic protection circuits.

4. The semiconductor device according to claim 1 , wherein

in a lower layer of the first bump electrodes which are connected to the remaining part, the internal circuit is disposed.

5. The semiconductor device according to claim 1 , wherein

the first bump electrodes are input bump electrodes.

6. The semiconductor device according to claim 1 , wherein

the semiconductor chip includes:

(d) a plurality of second bump electrodes arranged along a second long side and arranged at a position closer to the second long side than to the first long side; and

(e) a plurality of second electrostatic protection circuits which protect the internal circuit against static electricity and are electrically coupled to the second bump electrodes.

7. The semiconductor device according to claim 6 , wherein

the second bump electrodes and the internal circuit are electrically coupled via the second electrostatic protection circuits.

8. The semiconductor device according to claim 6 , wherein

in a lower layer of the second bump electrodes, the second electrostatic protection circuits are arranged.

9. The semiconductor device according to claim 6 , wherein

the second bump electrodes are output bump electrodes.

10. The semiconductor device according to claim 6 , wherein

the other first electrostatic protection circuits are arranged in an inner region sandwiched by a first region in which the first bump electrodes are formed and a second region in which the second bump electrodes are formed.

11. The semiconductor device according to claim 10 , wherein

the other first electrostatic protection circuits are divided and arranged in a plurality of regions within the inner region.

12. The semiconductor device according to claim 6 , wherein

the first bump electrodes are arranged linearly while the second bump electrodes are arranged in a staggered manner.

13. The semiconductor device according to claim 1 , wherein

the semiconductor chip is an LCD driver that drives a liquid crystal display device.

14. The semiconductor device according to claim 1 , wherein

in a lower layer of the other first bump electrodes, the other first electrostatic protection circuits are not arranged.

15. A semiconductor device comprising a semiconductor chip in the form of a rectangle having a first short side, a second short side in opposition to the first short side, a first long side, and a second long side in opposition to the first long side, wherein

the semiconductor chip includes:

(a) a first bump electrode and a second bump electrode arranged along the first long side of the semiconductor chip and arranged at a position closer to the first long side than to the second long side;

(b) an uppermost layer wiring disposed via an insulating film at a position that overlaps the first bump electrode and the second bump electrode in a planar view;

(c) a first opening formed in the insulating film and coupling the uppermost layer wiring to the first bump electrode; and

(d) a second opening formed in the insulating film and coupling the uppermost layer wiring to the second bump electrode, and wherein

a first position where the first opening is formed relative to the first bump electrode is different from a second position where the second opening is formed relative to the second bump electrode in a direction along the first short side or the second short side.

16. The semiconductor device according to claim 15 , wherein

the first position where the first opening is formed is closer to the first long side of the semiconductor chip than the second position where the second opening is formed.

17. The semiconductor device according to claim 15 , wherein

the uppermost layer wiring includes a first wiring which is coupled to the first bump electrode via the first opening and coupled to the second bump electrode via the second opening.

18. The semiconductor device according to claim 15 , wherein

the uppermost layer wiring includes:

a first uppermost layer wiring which is coupled to the first bump electrode via the first opening, passes under the second bump electrode, and is not coupled to the second bump electrode; and

a second uppermost layer wiring which is coupled to the second bump electrode via the second opening, passes under the first bump electrode, and is not coupled to the first bump electrode.

19. The semiconductor device according to claim 18 , wherein

the uppermost layer wiring further includes a third uppermost layer wiring which passes under the first bump electrode and the second bump electrode and is not coupled to the first bump electrode or to the second bump electrode.

20. The semiconductor device according to claim 15 , wherein

the semiconductor chip further includes an internal circuit formed in the semiconductor chip and a first electrostatic protection circuit that protects the internal circuit against static electricity; wherein

the first electrostatic protection circuit is electrically coupled between the first bump electrode and the internal circuit, and is formed in a region different from a region that overlaps the first bump electrode in a planar view; and wherein

the first bump electrode and the first electrostatic protection circuit are coupled by the uppermost layer wiring coupled to the first bump electrode via the first opening.

21. The semiconductor device according to claim 15 , wherein

the first bump electrode and the second bump electrode arranged along the first long side are a plurality of input bump electrodes, and wherein

a plurality of output bump electrodes is arranged in a staggered manner at a position closer to the second long side than to the first long side.

22. The semiconductor device according to claim 21 , wherein

respective areas of the input bump electrodes are greater than respective areas of the output bump electrodes.

23. The semiconductor device according to claim 21 , wherein

respective lengths in the short-side direction of the input bump electrodes are longer than respective lengths in the short-side direction of the output bump electrodes.

24. The semiconductor device according to claim 21 : wherein

the output bump electrodes arranged in a staggered manner have second output bump electrodes arranged at a position close to the second long side and first output bump electrodes arranged at a position farther from the second long side than the second output bump electrodes; wherein

a fourth uppermost layer wiring is formed under the first output bump electrode and a fifth uppermost layer wiring is formed under the second output bump electrode; wherein

the first output bump electrode is coupled to the fourth uppermost layer wiring via a third opening formed at a third position in the insulating film and the second output bump electrode is coupled to the fifth uppermost layer wiring via a fourth opening formed at a fourth position in the insulating film; and wherein

the third position where the third opening is formed is closer to the second long side than the center of the first output bump electrode and the fourth position where the fourth opening is formed is farther from the second long side than the center of the second output bump electrode.

25. A semiconductor device comprising a semiconductor chip in the form of a rectangle having a pair of short sides and a pair of long sides, wherein

the semiconductor chip includes:

a plurality of bump electrodes spaced apart from one another and arranged along a first long side of the semiconductor chip at a position closer to the first long side than to a second long side in opposition to the first long side; and

at least first and second uppermost layer wirings spaced apart from one another and overlapping said plurality of bump electrodes in a planar view of the semiconductor chip; wherein:

a first bump electrode of said plurality of bump electrodes is coupled to the first uppermost layer wiring by a first opening and to the second uppermost layer wiring by a second opening, the second opening being spaced apart from the first opening.

26. The semiconductor device according to claim 25 , further comprising:

an electrostatic protection circuit coupled to the first electrode by the second uppermost layer wiring; wherein:

the electrostatic protection circuit is arranged at a position different from a position that overlaps the first bump electrode, in a planar view of the semiconductor chip.

27. The semiconductor device according to claim 25 , wherein:

a second bump electrode of said plurality of bump electrodes is coupled to a third uppermost layer wiring by a third opening;

the third uppermost layer wiring overlaps the first bump electrode in a planar view of the semiconductor chip; and

the first bump electrode is not coupled to the third uppermost layer wiring by an opening.

28. The semiconductor device according to claim 25 , wherein:

a second bump electrode of said plurality of bump electrodes is coupled to the first uppermost layer wiring by a third opening; and

the second bump electrode is not coupled to the second uppermost layer wiring.

29. The semiconductor device according to claim 28 , wherein:

a third bump electrode of said plurality of bump electrodes is coupled to a third uppermost layer wiring by a fourth opening;

the third uppermost layer wiring overlaps both the first and second bump electrodes in a planar view of the semiconductor chip; and

neither the first bump electrode nor the second bump electrode is coupled to the third uppermost layer wiring by an opening.

30. The semiconductor device according to claim 29 , wherein:

a position where the third opening is formed relative to the second bump electrode is different from a position where the fourth opening is formed relative to the third bump electrode in the direction along the short sides.

31. The semiconductor device according to claim 30 , further comprising:

an electrostatic protection circuit coupled to the first electrode by the second uppermost layer wiring; wherein:

the electrostatic protection circuit is arranged at a position different from a position that overlaps any of the first, second and third bump electrodes, in a planar view of the semiconductor chip.

32. The semiconductor device according to claim 31 , further comprising:

at least one internal circuit formed in the semiconductor chip and arranged at a position that overlaps at least one or more of the first, second and third bump electrodes, in a planar view of the semiconductor chip.

33. The semiconductor device according to claim 32 , wherein the internal circuit is an SRAM.