Scalable non-blocking switching network for programmable logic
View Patent ↗A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
1. An integrated circuit, comprising a L-level permutable switching network (L-PSN);
wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:
wherein the (L+2) levels of conductors comprises:
for each i=[1:L], (I[i]/D [i])>1, D[1]>1, L≧1, at least one j where D[j]>2 for a j selected from j=[1:L], the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors,
wherein each of the D[i] sets of conductors comprises (I[i]/D[i]) number of conductors;
an 0-th level of conductors of I[0] number of conductors, wherein (I[0]/Π i=[1:L] D[i])>1;
an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,
wherein D[L+1]>2, each of the D[L+1] sets of conductors comprises (I[L+1]/D[L+1]) number of conductors and (I[L+1]/D[L+1])=Π i=[1:L] D[i];
wherein each i-th set of the (L+1) sets of switches comprises at least (T[i]×D[i]) number of switches for i=[1:L+1] where T[i]=(I[i−1]−D[i]+1);
wherein the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module selected from switching networks and logic cells;
wherein for each i=[1:L+1], at least T[i] number of conductors of the I[i−1] number of conductors of the (i−1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective plurality of at least T[i] number of switches of the i-th set of switches without requiring traversal of any other conductors.
2. The integrated circuit of claim 1 , wherein for at least one j selected from j=[1:L+1], each conductor of the (I[j]/D[j]) number of conductors in each of the D[j] sets of conductors selectively couples to at least (T[j]/(I[j]/D[j])) number of conductors of the at least T[j] number of conductors through a corresponding plurality of at least (T[j]/(I[j]/D[j])) number of switches without requiring traversal of any other conductors.
3. The integrated circuit of claim 1 , wherein for at least one j selected from j=[1:L+1], T[j]=I[j−1].
4. The integrated circuit of claim 3 , wherein each conductor of the (I[j]/D[j]) number of conductors in each of the D[j] sets of conductors selectively couples to at least (I[j−1]/I[j])×D[j] number of conductors of the I[j−1] number of conductors through a corresponding plurality of at least (I[j−1]/I[j])×D[j] number of switches without requiring traversal of any other conductors.
5. A method to manufacture an integrated circuit, comprising:
fabricating a L-level permutable switching network (L-PSN),
wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:
wherein the (L+2) levels of conductors comprises:
for each i=[1:L], (I[i]/D[i])>1, D[1]>1, L≧1, at least one j where D[j]>2 for a j selected from j=[1:L], the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors,
wherein each of the D[i] sets of conductors comprises (I[i]/D [i]) number of conductors;
an 0-th level of conductors of I[0] number of conductors, wherein (I[0]/Π i=[1:L] D[i])>1;
an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,
wherein D[L+1]>2, each of the D[L+1] sets of conductors comprises (I[L+1]/D[L+1]) number of conductors and (I[L+1]/D[L+1])=Π i=[1:L] D[i];
wherein each i-th set of the (L+1) sets of switches comprises at least (T[i]×D[i]) number of switches for i=[1:L+1] where T[i]=(I[i−1]−D[i]+1);
physically connecting the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors to a corresponding number of pins of a corresponding module selected from switching networks and logic cells; and
for each i=[1:L+1], selectively coupling at least T[i] number of conductors of the I[i−1] number of conductors of the (i−1)-th level of conductors to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective plurality of at least T[i] number of switches of the i-th set of switches without requiring traversal of any other conductors.
6. The method of claim 5 , further comprising: for at least one j selected from j=[1:L+1], selectively coupling each conductor of the (I[j]/D[j]) number of conductors in each of the D[j] sets of conductors to at least (T[j]/(I[j]/D[j])) number of conductors of the at least T[j] number of conductors through a corresponding plurality of at least (T[j]/(I[j]/D[j])) number of switches without requiring traversal of any other conductors.
7. The method of claim 5 , wherein for at least one j selected from j=[1:L+1], T[j]=I[j−1].
8. The method of claim 7 , further comprising selectively coupling each conductor of the (I[j]/D[j]) number of conductors in each of the D[j] sets of conductors to at least (I[j−1]/I[j])×D[j] number of conductors of the I[j−1] number of conductors through a corresponding plurality of at least (I[j−1]/I[j])×D[j] number of switches without requiring traversal of any other conductors.
9. An article of manufacture comprising a machine readable storage medium that stores data representing an integrated circuit layout, comprising: a L-level permutable switching network (L-PSN);
wherein the L-PSN comprises (L+2) levels of conductors and (L+1) sets of switches:
wherein the (L+2) levels of conductors comprises:
for each i=[1:L], (I[i]/D [i])>1, D[1]>1, L≧1, at least one j where D[j]>2 for a j selected from j=[1:L], the i-th level of conductors comprises I[i] number of conductors comprising D[i] sets of conductors,
wherein each of the D[i] sets of conductors comprises (I[i]/D [i]) number of conductors;
an 0-th level of conductors of I[0] number of conductors, wherein (I[0]/Π i=[1:L] D[i])>1;
an (L+1)-th level of conductors of I[L+1] number of conductors comprising D[L+1] sets of conductors,
wherein D[L+1]>2, each of the D[L+1] sets of conductors comprises (I[L+1]/D[L+1]) number of conductors and (I[L+1]/D[L+1])=Π i=[1:L] D[i];
wherein each i-th set of the (L+1) sets of switches comprises at least (T[i]×D[i]) number of switches for i=[ 1 :L+1] where T[i]=(I[i−1]−D[i]+1);
wherein the Π i=[1:L] D[i] number of conductors in each of the D[L+1] sets of conductors of the (L+1)-th level of conductors are physically connected to a corresponding number of pins of a corresponding module selected from switching networks and logic cells;
wherein for each i=[1:L+1], at least T[i] number of conductors of the I[i−1] number of conductors of the (i−1)-th level of conductors selectively couple to (I[i]/D[i]) number of conductors in each of the D[i] sets of conductors of the i-th level of conductors through a respective plurality of at least T[i] number of switches of the i-th set of switches without requiring traversal of any other conductors.
10. The article of manufacture of claim 9 , wherein for at least one j selected from j=[1:L+1], each conductor of the (I[j]/D[j]) number of conductors in each of the D[j] sets of conductors selectively couples to at least (T[j]/(I[j]/D[j])) number of conductors of the at least T[j] number of conductors through a corresponding plurality of at least (T[j]/(I[j]/D[j])) number of switches without requiring traversal of any other conductors.
11. The article of manufacture of claim 9 , wherein for at least one j selected from j=[1:L+1], T[j]=I[j−1].
12. The article of manufacture of claim 11 , wherein each conductor of the (I[j]/D[j]) number of conductors in each of the D[j] sets of conductors selectively couples to at least (I[j−1]/I[j])×D[j] number of conductors of the I[j−1] number of conductors through a corresponding plurality of at least (I[j−1]/I[j])×D[j] number of switches without requiring traversal of any other conductors.