System and method for extending the overload range of a sigma delta ADC system by providing over-range quantization levels
View Patent ↗Examples of a system and method for sigma-delta analog-to-digital conversion of an electrical input signal are disclosed. An electrical input signal is received. A filtered analog signal is provided based on the electrical input signal and an analog feedback signal. A digital representation of the filtered analog signal is provided, the digital representation being one of K quantization levels, wherein K is a positive integer between 2 L and 2 L+1 , L being a positive integer. The analog feedback signal is obtained based on the digital representation.
1. A sigma-delta analog-to-digital conversion system for data conversion of an electrical input signal, the system comprising:
a filter module configured to receive an electrical input signal and an analog feedback signal and to provide a filtered signal;
an extended-range multi-bit quantizer coupled to the filter module and configured to provide a digital representation of the filtered signal, the quantizer having K quantization levels, K being a positive integer between 2 L and 2 L+1 , L being a positive integer; and
a feedback digital-to-analog converter (DAC) module coupled to the extended-range multi-bit quantizer and configured to provide the analog feedback signal to the filter module, the feedback DAC module comprising a digital-to-analog converter configured to provide an analog representation of the digital representation,
wherein the extended-range multi-bit quantizer comprises a flash analog-to-digital converter.
2. The system of claim 1 , wherein L is 1, 2, 3, 4, or 5.
3. The system of claim 1 , wherein K=2 L +M, M being over-quantization levels provided in addition to 2 L quantization levels.
4. The system of claim 1 , wherein K=2 L+F , F being a fractional over-bit provided in addition to L integer bits.
5. The system of claim 1 , wherein the digital-to-analog converter comprises K quantization levels.
6. The system of claim 1 , wherein the filter module comprises a low-pass filter.
7. The system of claim 1 , wherein the filter module comprises a high-pass filter.
8. The system of claim 1 , wherein the filter module comprises a band-pass filter.
9. The system of claim 1 , wherein the filter module comprises a plurality of filter stages.
10. The system of claim 9 , wherein each of the plurality of filter stages comprises a filter and an amplifier.
11. The system of claim 1 , wherein the extended-range multi-bit quantizer comprises K comparator segments, each of the K comparator segments comprising a threshold reference, a two-input summing junction, an amplifier, and a limiter, wherein the two-input summing junction is configured to receive the filtered signal and a reference signal from the threshold reference, and to provide a summed signal that represents a sum of the filtered signal and the reference signal, the amplifier is configured to receive the summed signal and provide an amplified summed signal, and the limiter is configured to provide either −1 or +1 depending on whether the amplified summed signal is negative or positive.
12. The system of claim 1 , further comprising a processor configured to receive the digital representation and detect an overload condition based on the digital representation.
13. The system of claim 12 , further comprising a variable gain amplifier configured to vary an amplitude of an analog signal provided to the extended-range multi-bit quantizer, wherein the processor is further configured to reduce a gain of the variable gain amplifier if the overload condition is detected.
14. A method of performing a sigma-delta analog-to-digital conversion of an electrical input signal, the method comprising:
receiving an electrical input signal;
providing a filtered analog signal based on the electrical input signal and an analog feedback signal;
providing a digital representation of the filtered analog signal, the digital representation being one of K quantization levels, wherein K is a positive integer between 2 L and 2 L+1 , L being a positive integer, and wherein K=2 L +M, M being over-quantization levels provided in addition to 2 L quantization levels; and
obtaining the analog feedback signal based on the digital representation.
15. The method of claim 14 , wherein the obtaining comprises performing a digital-to-analog conversion of the digital representation.
16. The method of claim 14 , further comprising determining whether an overload condition exists based on the digital representation.
17. The method of claim 16 , wherein the determining comprises comparing the digital representation to 2 L .
18. The method of claim 14 , wherein the filtering comprises low-pass filtering.
19. The method of claim 14 , wherein the filtering comprises band-pass filtering.
20. The method of claim 14 , wherein the providing the digital representation comprises:
producing a sum of the filtered analog signal and a threshold reference value;
providing a comparison output value based on the sum, the comparison output value being positive if the sum is greater than zero and negative if the sum is less than zero;
amplifying the comparison output value; and
limiting the comparison output value after the amplification to one of +1 and −1.
21. The method of claim 14 , wherein the filtering comprises high-pass filtering.