IP Library Granted Patent US 8,090,047
Granted Patent B2
US 8,090,047 · App. 12/795,808 · Granted Jan 3, 2012

System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system

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Quick Facts
Patent No.
US 8,090,047
App. No.
12/795,808
Granted
Jan 3, 2012
Kind
B2
Abstract

Systems and methods for optimizing operation of a transceiver device are disclosed. The method may include parallel processing an input signal through a first path having a first frequency response and a second path having a second frequency response. The second frequency response may be higher than the first frequency response. Signals from the first and second paths may be combined, creating an output signal having a desired gain and frequency. The parallel processing may adjust a gain of at least one of the first path and the second path. The parallel processing may equalize at least one of the first frequency response and the second frequency response. The input signal may be from a 10 GBit Ethernet channel and/or a Fibre channel.

Claims (32)

1. A method for optimizing operation of a transceiver device, the method comprising:

dividing an input signal into a first signal portion and a second signal portion based on a select signal, said select signal comprising a plurality of select levels;

parallel processing said first signal portion through a first path having a first frequency response, and said second signal portion through a second path having a second frequency response, wherein the second frequency response is higher than the first frequency response; and

combining signals from the first and second paths, creating an output signal having a desired gain and frequency.

2. The method according to claim 1 , wherein the parallel processing adjusts a gain of at least one of the first path and the second path.

3. The method according to claim 2 , wherein the parallel processing equalizes at least one of the first frequency response and the second frequency response.

4. The method according to claim 1 , wherein the input signal is from a 10 GBit Ethernet channel.

5. The method according to claim 1 wherein the input signal is from a Fibre channel.

6. A system for optimizing operation of a transceiver device, the system comprising:

a divider operable to divide an input signal into a first signal portion and a second signal portion based on a select signal, said select signal comprising a plurality of select levels;

a parallel processor operable to process said first signal portion through a first path having a first frequency response, and said second signal portion through a second path having a second frequency response, wherein the second frequency response is higher than the first frequency response; and

a combiner for combining signals from the first and second paths, creating an output signal having a desired gain and frequency.

7. The system according to claim 6 , wherein the parallel processor is operable to adjust a gain of at least one of the first path and the second path.

8. The system according to claim 6 , wherein the parallel processor is operable to equalize at least one of the first frequency response and the second frequency response.

9. The system according to claim 6 , wherein the input signal is from a 10 GBit Ethernet channel.

10. The system according to claim 6 , wherein the input signal is from a Fibre channel.

11. A system for optimizing operation of a transceiver device, the system comprising:

one or more circuits that are operable to divide an input signal into a first signal portion and a second signal portion based on a select signal, said select signal comprising a plurality of select levels;

said one or more circuits are operable to parallel process said first signal portion through a first path having a first frequency response, and said second signal portion through a second path having a second frequency response, wherein the second frequency response is higher than the first frequency response; and

said one or more circuits are operable to combine signals from the first and second paths, creating an output signal having a desired gain and frequency.

12. The system according to claim 11 , wherein the parallel processing adjusts a gain of at least one of the first path and the second path.

13. The system according to claim 12 , wherein the parallel processing equalizes at least one of the first frequency response and the second frequency response.

14. The system according to claim 11 , wherein the input signal is from a 10 GBit Ethernet channel.

15. The system according to claim 11 , wherein the input signal is from a Fibre channel.

16. A system for optimizing operation of a transceiver device, the system comprising:

at least one processor that enables dividing an input signal into a first signal portion and a second signal portion based on a select signal, said select signal comprising a plurality of select levels;

said at least one processor enables parallel processing of said first signal portion through a first path having a first frequency response, and said second signal portion through a second path having a second frequency response, wherein the second frequency response is higher than the first frequency response; and

said at least one processor enables combining of signals from the first and second paths, creating an output signal having a desired gain and frequency.

17. The system according to claim 16 , wherein the parallel processing adjusts a gain of at least one of the first path and the second path.

18. The system according to claim 17 , wherein the parallel processing equalizes at least one of the first frequency response and the second frequency response.

19. The system according to claim 16 , wherein the input signal is from a 10 GBit Ethernet channel.

20. The system according to claim 16 , wherein the input signal is from a Fibre channel.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2011
From: FUJIMORI, ICHIRO; TONIETTO, DAVIDE
To: BROADCOM CORPORATION
Reel/Frame 027283/0277 →