IP Library Granted Patent US 8,355,105
Granted Patent B2
US 8,355,105 · App. 12/796,805 · Granted Jan 15, 2013

Array substrate for liquid crystal panel and liquid crystal panel

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Quick Facts
Patent No.
US 8,355,105
App. No.
12/796,805
Granted
Jan 15, 2013
Kind
B2
Abstract

An array substrate for a liquid crystal panel includes a plurality of pixel electrodes corresponding to a plurality of pixels, and a common electrode provided common to the plurality of pixel electrodes. An alignment of liquid crystal is controlled by each electric field between each of the plurality of the pixel electrodes and the common electrode. The array substrate further includes a pixel selecting circuit, a line group for pixel selecting circuit, a potential applying circuit, a line group for potential applying circuit, and a common electrode line. The pixel selecting circuit sequentially selects pixels among the plurality of pixels. The line group for pixel selecting circuit is connected to input terminals of the pixel selecting circuit. The potential applying circuit applies a potential to the pixel electrode of a selected pixel. The line group for potential applying circuit is connected to input terminals of the potential applying circuit. The common electrode line is connected to the common electrode. The common electrode line extends in a region between the pixel selecting circuit and the potential applying circuit and in a region between the line group for pixel selecting circuit and the line group for potential applying circuit.

Claims (38)

1. An array substrate for a liquid crystal panel, the array substrate comprising:

pixel electrodes corresponding to pixels;

a common electrode that is common to all of the pixel electrodes and that is capable of forming an electric field that controls an alignment of liquid crystal in conjunction with each of the pixel electrodes;

a single pixel selecting circuit positioned on only one side of the common electrode and that sequentially selects the pixels;

a line group for the pixel selecting circuit connected to input terminals of the pixel selecting circuit;

a potential applying circuit that applies a potential to the pixel electrode of a selected pixel;

a line group for the potential applying circuit connected to input terminals of the potential applying circuit; and

a common electrode line connected to the common electrode and arranged so as to avoid crossing the line group for the pixel selecting circuit and the line group for the potential applying circuit,

wherein the common electrode line extends between the line group for the pixel selecting circuit and the line group for the potential applying circuit, and extends into a terminal region along a routing path, and the arrangement and position of the line group for the potential applying circuit is such that it does not intersect with an area encompassed by the routing path of the common electrode line.

2. The array substrate for a liquid crystal panel according to claim 1 , wherein the terminal region includes end portions of each of the common electrode line, the line group for the pixel selecting circuit, and the line group for the potential applying circuit.

3. The array substrate for a liquid crystal panel according to claim 1 , wherein one end of the common electrode line is connected to the common electrode near a corner portion of an array of the pixels, the corner portion being adjacent to both the pixel selecting circuit and the potential applying circuit.

4. The array substrate for a liquid crystal panel according to claim 1 , wherein the common electrode line is connected to the common electrode at a single location.

5. The array substrate for a liquid crystal panel according to claim 1 , wherein the line group for the potential applying circuit extends from a first side of the potential applying circuit, and the common electrode line is routed around a second side of the potential applying circuit that is opposite to the first side of the potential applying circuit.

6. The array substrate for a liquid crystal panel according to claim 1 , wherein:

each of the terminal portions of the line group for the pixel selecting circuit are arranged on a first side of the terminal region,

each of the terminal portions of the line group for the potential applying circuit are arranged on a second side of the terminal region opposite to the first side, and

the terminal portion of the common electrode line is arranged in the terminal region between the terminal portions of the line group for the pixel selecting circuit and the terminal portions of the line group for the potential applying circuit.

7. A liquid crystal panel comprising:

an array substrate including pixel electrodes corresponding to pixels, and also including a common electrode that is common to all of the pixel electrodes and that is capable of forming an electric field that controls an alignment of liquid crystal in conjunction with each of the pixel electrodes;

an opposing substrate placed opposing the array substrate; and

liquid crystal held between the array substrate and the opposing substrate, an alignment of which is controlled by an electric field between each of the pixel electrodes and the common electrode, wherein

the array substrate further includes:

a single pixel selecting circuit positioned on only one side of the common electrode and that sequentially selects the pixels;

a line group for the pixel selecting circuit connected to input terminals of the pixel selecting circuit;

a potential applying circuit that applies a potential to the pixel electrode of a selected pixel;

a line group for the potential applying circuit connected to input terminals of the potential applying circuit; and

a common electrode line connected to the common electrode and arranged so as to avoid crossing the line group for the pixel selecting circuit and the line group for the potential applying circuit,

wherein the common electrode line extends between the line group for the pixel selecting circuit and the line group for the potential applying circuit, and is routed into a terminal region along a routing path, and the arrangement and position of the line group for the potential applying circuit is such that it does not intersect with an area encompassed by the routing path of the common electrode line.

8. The liquid crystal panel according to claim 7 , further comprising:

an integrated circuit chip mounted on the array substrate and connected to the common electrode line, the line group for the pixel selecting circuit, and the line group for the potential applying circuit, wherein the common electrode line connects the integrated circuit chip and the common electrode.

9. The liquid crystal panel according to claim 7 , wherein the terminal region includes end portions of each of the common electrode line, the line group for the pixel selecting circuit, and the line group for the potential applying circuit.

10. The liquid crystal panel according to claim 7 , wherein one end of the common electrode line is connected to the common electrode near a corner portion of an array of the pixels, the corner portion being adjacent to both the pixel selecting circuit and the potential applying circuit.

11. The liquid crystal panel according to claim 7 , wherein the common electrode line is connected to the common electrode at a single location.

12. The liquid crystal panel according to claim 7 , wherein the line group for the potential applying circuit extends from a first side of the potential applying circuit, and the common electrode line is routed around a second side of the potential applying circuit that is opposite to the first side of the potential applying circuit.

13. The liquid crystal panel according to claim 7 , wherein:

each of the terminal portions of the line group for the pixel selecting circuit are arranged on a first side of the terminal region,

each of the terminal portions of the line group for the potential applying circuit are arranged on a second side of the terminal region opposite to the first side, and

the terminal portion of the common electrode line is arranged in the terminal region between the terminal portions of the line group for the pixel selecting circuit and the terminal portions of the line group for the potential applying circuit.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072398/0001 →
MERGER AND CHANGE OF NAME Recorded Jul 24, 2025
From: JAPAN DISPLAY EAST INC.; JAPAN DISPLAY WEST INC.
To: JAPAN DISPLAY INC.
Reel/Frame 071935/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2013
From: SONY CORPORATION
To: JAPAN DISPLAY WEST INC.
Reel/Frame 030182/0522 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2011
From: EPSON IMAGING DEVICES CORPORATION
To: SONY CORPORATION
Reel/Frame 025935/0327 →