Information processing device, image display device, and information processing method

1. An information processing device comprising:

a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access; and

a second processing unit accessible by the first processing unit by a first access method or a second access method, the second processing unit including:

a control register accessible by the first processing unit,

a data buffer accessible by the first processing unit,

a host controller that has a plurality of interface circuits connected with a serial bus, and

an arbiter that arbitrates transmission of read data or write data between the control register, the data buffer, and the host controller;

wherein

when asserting the first chip select signal, the first processing unit accesses the second processing unit by the first access method,

when asserting the second chip select signal, the first processing unit accesses the second processing unit by the second access method,

the data buffer buffers data transmitted via the serial bus connected with respective interface circuits included in the plural interface circuits; and

serial/parallel conversion or parallel/serial conversion of the data transmitted via the serial bus connected with the interface circuits included in the plural interface circuits and arbitrated by the arbiter is performed.

2. The information processing device according to claim 1 , wherein:

when asserting the first chip select signal, the first processing unit performs register access for accessing the control register; and

when asserting the second chip select signal, the first processing unit performs block access which repeatedly designates successive addresses for accessing the data buffer.

3. The information processing device according to claim 1 , further comprising:

a supplementary processing unit which has a decoder for decoding the first chip select signal, the second chip select signal, and the address corresponding to the address space accessed by the first processing unit,

wherein the supplementary processing unit selects the second processing unit based on a decode result from the decoder.

4. The information processing device according to claim 3 , wherein the supplementary processing unit switches between change timing of an access control signal outputted to the second processing unit by the first access method and change timing of an access control signal outputted to the second processing unit by the second access method based on the decode result from the decoder.

5. The information processing device according to claim 3 , wherein types of access control signal used in the first access method and the second access method are switched based on the decode result from the decoder.

6. An image display device which displays an image corresponding to image data, comprising:

the information processing device according to claim 5 which receives image data as serial data via a device connected with the second processing unit and outputs the image data converted into parallel data;

an image processing unit which performs image processing for the image data received from the information processing device; and

an image display unit which displays an image corresponding to the image data after the image processing by the image processing unit.

7. An information processing method for an information processing device having a first processing unit and a second processing unit accessed by the first processing unit, the second processing unit including a control register accessible by the first processing unit, a data buffer accessible by the first processing unit, a host controller that has a plurality of interface circuits connected with a serial bus, and an arbiter that arbitrates transmission of read data or write data between the control register, the data buffer, and the host controller, the method comprising:

allowing the first processing unit to assert a first chip select signal or a second chip select signal according to an address space to be accessed;

allowing the first processing unit to access the second processing unit by an access method corresponding to the chip select signal asserted by the first processing unit:,

buffering data transmitted via the serial bus connected with respective interface circuits included in the plural interface circuits; and

performing serial/parallel conversion or parallel/serial conversion of the data transmitted via the serial bus connected with the interface circuits included in the plural interface circuits and arbitrated by the arbiter,

wherein the first processing unit accesses the second processing unit by a first access method when asserting the first chip select signal, and accesses the second processing unit when asserting the second chip select signal.

8. An information processing device comprising:

a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access;

a second processing unit accessible by the first processing unit by a first access method or a second access method; and

a supplementary processing unit that has a decoder for decoding the first chip select signal, the second chip select signal, and the address corresponding to the address space accessed by the first processing unit,

wherein

when asserting the first chip select signal, the first processing unit accesses the second processing unit by the first access method,

when asserting the second chip select signal, the first processing unit accesses the second processing unit by the second access method, and

the supplementary processing unit switches between change timing of an access control signal outputted to the second processing unit by the first access method and change timing of an access control signal outputted to the second processing unit by the second access method based on a decode result from the decoder.

9. An information processing method for an information processing device having a first processing unit, a second processing unit accessed by the first processing unit, and a supplementary processing unit that has a decoder, comprising:

allowing the first processing unit to assert a first chip select signal or a second chip select signal according to an address space to be accessed;

allowing the first processing unit to access the second processing unit by an access method corresponding to the chip select signal asserted by the first processing unit;

decoding the first chip select signal, the second chip select signal, and the address corresponding to the address space accessed by the first processing unit; and

switching between change timing of an access control signal outputted to the second processing unit by the first access method and change timing of an access control signal outputted to the second processing unit by the second access method based on a decode result from the decoder,

wherein the first processing unit accesses the second processing unit by a first access method when asserting the first chip select signal, and accesses the second processing unit when asserting the second chip select signal.