IP Library Granted Patent US 8,319,113
Granted Patent B2
US 8,319,113 · App. 12/797,244 · Granted Nov 27, 2012

Printed circuit board with reduced dielectric loss

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Quick Facts
Patent No.
US 8,319,113
App. No.
12/797,244
Granted
Nov 27, 2012
Kind
B2
Abstract

A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.

Claims (17)

1. A printed circuit board (‘PCB’) with reduced dielectric loss, the PCB comprising:

conductive traces disposed upon layers of dielectric material; and

the layers of dielectric material, including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB, wherein:

the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another; and

the pockets of air are aligned at an angle of 45 degrees with respect to the conductive traces.

2. The PCB of claim 1 wherein the pockets of air are aligned with at least some of the conductive traces.

3. The PCB of claim 1 wherein the layers of dielectric material that include pockets of air are prepreg layers only.

4. The PCB of claim 1 wherein the layers of dielectric material that include pockets of air comprise both prepreg layers and core layers.

5. A printed circuit board (‘PCB’) with reduced dielectric loss, the PCB comprising:

conductive traces disposed upon layers of dielectric material; and

the layers of dielectric material, including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB, wherein:

at least some of the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another;

at least some of the conductive traces are disposed upon layers of the dielectric material at an angle of 45 degrees with respect to the orthogonal traces; and

the pockets of air are aligned at an angle of 22.5 degrees with respect to at least some of the orthogonal traces.

6. The PCB of claim 5 wherein the pockets of air are aligned with at least some of the conductive traces.

7. The PCB of claim 5 wherein the layers of dielectric material that include pockets of air are prepreg layers only.

8. The PCB of claim 5 wherein the layers of dielectric material that include pockets of air comprise both prepreg layers and core layers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: LENOVO INTERNATIONAL LIMITED
Reel/Frame 034194/0291 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2010
From: CASES, MOISES; HERRMAN, BRADLEY D.; MUTNURY, BHYRAV M.; PHAM, NAM H.; RODRIGUES, TERENCE
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 024513/0916 →