Method for fabrication of a semiconductor device and structure
View Patent ↗A configurable integrated circuit (IC) system comprising: a first die comprising input/output cells; and a configurable logic second die connected by a first plurality of through-silicon-vias (TSVs) to the first die.
1. A configurable integrated circuit (IC) system comprising:
a first die comprising input/output cells; and
a Field Programmable Gated Array (FPGA) second die substantially vertically connected by a first plurality of through-silicon-vias (TSVs) to the first die, wherein said FPGA second die comprises a plurality of unused predetermined dice lines, wherein said FPGA second die comprises at least two micro control units (MCUs), and at least one permanent connection to electrically interconnect said micro control units.
2. A configurable IC system according to claim 1 , wherein said first die is fabricated by a process older than said FPGA second die.
3. A configurable IC system according to claim 1 , further comprising:
a third die connected to at least one of said first die or said FPGA second die by a second plurality of through silicon-vias (TSVs).
4. A configurable IC system according to claim 1 , wherein said first die further comprises serializer/deserializer (SerDes) circuits.
5. A configurable IC system according to claim 1 , wherein said FPGA second die comprises:
a plurality of configurable logic cells, and
between one and two metal layers interconnecting said configurable logic cells across said unused predetermined dice lines.
6. A configurable IC system comprising:
a first die comprising input/output cells; and
a Field Programmable Gated Array (FPGA) second die connected by a first plurality of through-silicon-vias (TSV) to the first die;
wherein said FPGA second die comprises at least two micro control units (MCUs), and said FPGA second die further comprises at least one permanent connection to electrically interconnect said micro control units.
7. A configurable IC system according to claim 6 , wherein said FPGA second die comprises a plurality of unused predetermined dice lines.
8. A configurable IC system according to claim 6 , wherein said first die is fabricated in a process older than said FPGA second die.
9. A configurable IC system according to claim 6 wherein said FPGA second die further comprises a plurality of memory circuits.
10. A configurable IC system according to claim 6 , wherein said first die further comprises serializer/deserializer (SerDes) circuits.
11. A configurable IC system according to claim 7 , wherein said FPGA second die comprises a plurality of configurable logic cells and between one and two metal layers interconnecting said configurable logic cells across said unused predetermined dice lines.
12. The configurable IC system according to claim 6 , wherein said permanent connection is made before said FPGA second die is connected to said first die by said first plurality of TSVs.
13. The configurable IC system according to claim 1 , wherein said plurality of unused predetermined dice lines allow FPGA dies of multiple die sizes to be constructed based on the same mask set.