IP Library Granted Patent US 8,299,527
Granted Patent B2
US 8,299,527 · App. 12/800,037 · Granted Oct 30, 2012

Vertical LDMOS device and method for fabricating same

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Quick Facts
Patent No.
US 8,299,527
App. No.
12/800,037
Granted
Oct 30, 2012
Kind
B2
Abstract

A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body.

Claims (19)

1. A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprising:

a trench within a semiconductor body, and a semiconductor substrate underlying said semiconductor body, said trench including sidewalls, a bottom portion, a dielectric material lining said trench and a diffusion agent layer lining said dielectric material;

a lightly doped drain region extending laterally from said sidewalls of said trench into said semiconductor body.

2. The vertically arranged LDMOS device of claim 1 , further comprising an insulative material filling said trench.

3. The vertically arranged LDMOS device of claim 1 , wherein said semiconductor body is of a first conductivity type, and said lightly doped drain region and said semiconductor substrate are of a second conductivity type.

4. The vertically arranged LDMOS device of claim 1 , wherein said trench further comprises a gate electrode formed over said diffusion agent layer.

5. The vertically arranged LDMOS device of claim 1 , wherein said trench extends into said semiconductor substrate.

6. The vertically arranged LDMOS device of claim 1 , wherein said bottom portion of said trench is disposed above said semiconductor substrate.

7. The vertically arranged LDMOS device of claim 1 , wherein said lightly doped drain region extends to said semiconductor substrate.

8. The vertically arranged LDMOS device of claim 1 , wherein said semiconductor body comprises an epitaxial semiconductor layer.

9. A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprising:

first and second trenches each extending into a semiconductor body, and a semiconductor substrate underlying said semiconductor body;

a first lightly doped drain region adjoining said first trench and a second lightly doped drain region adjoining said second trench;

wherein said first and second lightly doped drain regions are spaced laterally apart by said semiconductor body.

10. The vertically arranged LDMOS device of claim 9 , wherein said first and second trenches each includes sidewalls, a bottom portion, a dielectric material lining each trench and a diffusion agent layer lining said dielectric material;

said first and second lightly doped drain regions extending laterally from said sidewalls of said trenches into said semiconductor body.

11. The vertically arranged LDMOS device of claim 9 , wherein said semiconductor body is of a first conductivity type, and said first and second lightly doped drain regions and said semiconductor substrate are of a second conductivity type.

12. The vertically arranged LDMOS device of claim 9 , wherein said first and second trenches extend into said semiconductor substrate.

13. The vertically arranged LDMOS device of claim 9 , wherein said bottom portion of each of said first and second trenches is disposed above said semiconductor substrate.

Assignments (2)
CHANGE OF NAME Recorded Jul 23, 2018
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 046612/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2011
From: BOL, IGOR
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 025601/0814 →