Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
View Patent ↗Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
1. A method for compensating parasitic capacitances, comprising:
providing a plurality of stacked switches, the stacked switches proceeding from a first switch closest to a first terminal and farthest from a second terminal to an n-th switch farthest from the first terminal and closest to the second terminal, the first terminal being a terminal through which a voltage source is adapted to be coupled to the stacked switches;
sizing the stacked switches so that the first switch has the same size of the n-th switch; and
further sizing the stacked switches so that the i-th switch (i=2, 3, 4, . . . ) has the same size of the (n−i+1)-th switch,
wherein the sized first and n-th switches are larger than the sized second and (n−1)-th switches, and so on.
2. The method of claim 1 , wherein the first terminal is an RF terminal and the second terminal is an RF terminal.
3. A method for compensating parasitic capacitances, comprising:
providing a plurality of stacked switches, the stacked switches proceeding from a first switch closest to a first terminal and farthest from a second terminal to an n-th switch farthest from the first terminal and closest to the second terminal, the first terminal being a terminal through which a voltage source is adapted to be coupled to the stacked switches; and
sizing the stacked switches so that the first switch has the same size of the n-th switch,
wherein:
the first terminal is an RF terminal and the second terminal is an RF terminal, and
the plurality of stacked switches is part of a unit cell for a significant bit sub-circuit of a digitally tunable capacitor (DTC), the significant bit sub-circuit being coupled between the first RF terminal and the second RF terminal.
4. The method of claim 1 , further comprising:
coupling the plurality of stacked switches in series with one or more metal-insulator-metal (MIM) capacitor or metal-metal (MM) capacitor.
5. The method of claim 1 , wherein the second terminal is ground.
6. A stacked device comprising:
a plurality of stacked switches, the stacked switches proceeding from a first switch closest to a first terminal and farthest from a second terminal to an n-th switch farthest from the first terminal and closest to the second terminal, the first terminal being a terminal through which a voltage source is adapted to be coupled to the stacked switches, the stacked switches being sized such that the first and the n-th switch have the same size and such that the i-th switch (i=2, 3, 4, . . . ) has the same size of the (n−i+1)-th switch,
wherein the sized first and n-th switches are larger than the sized second and (n−1)-th switches, and so on.
7. The stacked device of claim 6 , wherein the first terminal is an RF terminal and the second terminal is an RF terminal.
8. The stacked device of claim 6 , further comprising:
one or more metal-insulator-metal (MIM) capacitor or metal-metal (MM) capacitor coupled in series with the plurality of stacked switches.
9. The stacked device of claim 6 , wherein the second terminal is ground.
10. A stacked device comprising:
a plurality of stacked switches, the stacked switches proceeding from a first switch closest to a first terminal and farthest from a second terminal to an n-th switch farthest from the first terminal and closest to the second terminal, the first terminal being a terminal through which a voltage source is adapted to be coupled to the stacked switches, the stacked switches being sized such that the first and the n-th switch have the same size,
wherein:
the first terminal is an RF terminal and the second terminal is an RF terminal, and
the plurality of stacked switches is part of a unit cell for a significant bit sub-circuit of a digitally tunable capacitor (DTC), the significant bit sub-circuit being coupled between the first RF terminal and the second RF terminal.