IP Library Granted Patent US 8,471,585
Granted Patent B2
US 8,471,585 · App. 12/805,273 · Granted Jun 25, 2013

Method for evaluating semiconductor device

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Quick Facts
Patent No.
US 8,471,585
App. No.
12/805,273
Granted
Jun 25, 2013
Kind
B2
Abstract

A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.

Claims (14)

1. A method for evaluating a semiconductor device, comprising:

fixing a sheet having electrical conductivity to a first surface layer of a semiconductor substrate where a plurality of semiconductor devices is formed, the plurality of semiconductor devices having a surface structure in a second surface layer of the semiconductor substrate and a rear surface electrode in the first surface layer;

dividing the semiconductor substrate into semiconductor chips on a first support stage in the state where the sheet is fixed to the first surface layer; and

mounting the plurality of divided semiconductor chips on the sheet on a second support stage, and continuously subjecting the plurality of mounted semiconductor chips to a dynamic characteristic test on the second support stage, wherein a current is able to flow from the second stage and between the rear surface electrode and the sheet.

2. The method according to claim 1 , wherein:

the sheet comprises a resin and an adhesive member including metal powder.

3. The method according to claim 1 , wherein:

the dynamic characteristic test comprises bringing a probe pin into contact with a control electrode or main electrode of at least one of the semiconductor chips that are mounted on the second support stage via the sheet, performing a continuous operation for turning on or off the control electrode, and energizing or disconnecting a current between the main electrode and the rear surface electrode.

4. The method according to claim 1 , wherein:

the current that flows from the second support stage to the semiconductor chips via the sheet is 0 to several thousand amperes.

5. The method according to claim 1 , wherein:

the semiconductor substrate is divided into the semiconductor chips with a dicing blade, and the semiconductor chips are subjected to the dynamic characteristic test by a prober.

6. The method according to claim 1 , wherein:

in dividing the semiconductor substrate into the semiconductor chips, a dicing blade makes a cut only to an interface between the semiconductor substrate and the sheet, or to a position where the dicing blade slightly penetrates the sheet in a thickness direction of the sheet.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Aug 26, 2011
From: FUJI ELECTRIC SYSTEMS CO., LTD. (FES); FUJI TECHNOSURVEY CO., LTD. (MERGER BY ABSORPTION)
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 026970/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2010
From: MIYAZONO, MITSUYOSHI; KOMATSU, SHIGEKAZU; SHINOZAKI, DAI; KATO, MASAHIRO; YOSHIDA, ATSUSHI
To: TOKYO ELECTRON LIMITED; FUJI ELECTRIC SYSTEMS CO., LTD.,
Reel/Frame 025133/0884 →