Organic light emitting diode display and method of manufacturing the same

1. An organic light emitting diode display, comprising:

a substrate main body;

a first gate electrode and a second semiconductor layer on the substrate main body;

a gate insulating layer on the first gate electrode and the second semiconductor layer;

a first semiconductor layer and a second gate electrode on the gate insulating layer, the first semiconductor layer overlying the first gate electrode and the second gate electrode overlying the second semiconductor layer;

a plurality of etching stopper layers, the plurality of etching stopper layers contacting portions of the first semiconductor layer;

an interlayer insulating layer on the first semiconductor layer and the second gate electrode, the interlayer insulating layer including a plurality of contact holes exposing the plurality of etching stopper layers, respectively;

a first source electrode and a first drain electrode on the interlayer insulating layer and the contact holes, the first source electrode and the first drain electrode being indirectly connected to the first semiconductor layer via the plurality of etching stopper layers or directly connected to the first semiconductor layer; and

a second source electrode and a second drain electrode on the interlayer insulating layer, the second source electrode and the second drain electrode being connected to the second semiconductor layer.

2. The organic light emitting diode display as claimed in claim 1 , wherein the first semiconductor layer is an oxide semiconductor layer.

3. The organic light emitting diode display as claimed in claim 2 , wherein the etching stopper layers are disposed external to the first semiconductor layer.

4. The organic light emitting diode display as claimed in claim 2 , wherein the second semiconductor layer includes:

a channel region under the second gate electrode, and

source and drain regions at respective sides of the channel region.

5. The organic light emitting diode display as claimed in claim 4 , wherein:

the channel region of the second semiconductor layer includes a non-doped polycrystalline silicon layer, and

the source and drain regions of the second semiconductor layer include an impurity-doped polycrystalline silicon layer.

6. The organic light emitting diode display as claimed in claim 5 , wherein the first gate electrode includes the same material as, and is disposed in the same plane as, the source and drain regions of the second semiconductor layer.

7. The organic light emitting diode display as claimed in claim 4 , wherein:

the interlayer insulating layer and the gate insulating layer further include additional contact holes, the additional contact holes partially exposing the source and drain regions of the second semiconductor layer; and

the second source electrode and second drain electrode are disposed in respective additional contact holes.

8. The organic light emitting diode display as claimed in claim 1 , wherein the etching stopper layers are disposed directly on portions of the first semiconductor layer.

9. The organic light emitting diode display as claimed in claim 8 , wherein the second gate electrode includes:

a first electrode layer, the first electrode layer including the same material as the first semiconductor layer, and

a second electrode layer, the second electrode layer including the same material as the etching stopper layer.

10. The organic light emitting diode display as claimed in claim 1 , wherein portions of the first semiconductor layer are disposed directly on portions of the etching stopper layers.

11. The organic light emitting diode display as claimed in claim 10 , wherein the second gate electrode includes the same material as the etching stopper layers.

12. A method of manufacturing an organic light emitting diode display, the method comprising:

forming a first gate electrode precursor and a second semiconductor layer precursor on a substrate main body such that the first gate electrode precursor and the second semiconductor layer each include a polycrystalline silicon layer;

forming a gate insulating layer on the first gate electrode precursor and the second semiconductor layer precursor;

sequentially forming an oxide semiconductor layer and a metallic layer on the gate insulating layer;

patterning the oxide semiconductor layer and the metallic layer to form a second gate electrode, a first semiconductor layer, and a plurality of etching stopper layers such that the plurality of etching stopper layers are disposed directly on portions of the first semiconductor layer;

doping impurities into the first gate electrode precursor and the second semiconductor layer precursor to form a first gate electrode and a second semiconductor layer;

forming an interlayer insulating layer on the second gate electrode, the first semiconductor layer, and the etching stopper layers;

etching the interlayer insulating layer to form a first source contact hole and a first drain contact hole exposing the plurality of etching stopper layers, respectively; and

etching the interlayer insulating layer and the gate insulating layer together to form a second source contact hole and a second drain contact hole partially exposing the second semiconductor layer.

13. The method as claimed in claim 12 , further comprising forming a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode on the interlayer insulating layer, and wherein:

the first source electrode and the first drain electrode are directly connected to the first semiconductor layer via the first source and first drain contact holes or indirectly connected to the first semiconductor layer via the etching stopper layers, and

the second source electrode and the second drain electrode are connected to the second semiconductor layer through the second source contact hole and the second drain contact hole, respectively.

14. The method as claimed in claim 13 , wherein the etching stopper layers are disposed external to the first semiconductor layer.

15. The method as claimed in claim 13 , wherein the second semiconductor layer includes:

a channel region, the channel region being disposed under the second gate electrode, and

source and drain regions, the source and drain regions being disposed at respective sides of the channel region.

16. The method as claimed in claim 15 , wherein the channel region of the second semiconductor layer includes a non-doped polycrystalline silicon layer and the source and drain regions of the second semiconductor layer include an impurity-doped polycrystalline silicon layer.

17. The method as claimed in claim 16 , wherein the first gate electrode is formed in the same way as, in the same plane as, and of the same material as the source and drain regions of the second semiconductor layer.

18. The method as claimed in claim 12 , wherein the second gate electrode includes a double-layered structure formed from the oxide semiconductor layer and the metallic layer, wherein the first semiconductor layer is formed from the oxide semiconductor layer, and wherein the etching stopper layers are formed from the metallic layer.

19. A method of manufacturing an organic light emitting diode display, the method comprising:

forming a first gate electrode precursor and a second semiconductor layer precursor on a substrate main body such that the first gate electrode precursor and second semiconductor layer precursor include a polycrystalline silicon layer;

forming a gate insulating layer on the first gate electrode precursor and the second semiconductor layer precursor;

forming a metallic layer on the gate insulating layer;

patterning the metallic layer to form a second gate electrode and a plurality of etching stopper layers;

doping impurities into the first gate electrode precursor and the second semiconductor layer precursor to form a first gate electrode and a second semiconductor layer;

forming an oxide semiconductor layer on the plurality of etching stopper layers;

patterning the oxide semiconductor layer to form a first semiconductor layer such that portions of the first semiconductor layer at least partially overlie portions of the etching stopper layers;

forming an interlayer insulating layer on the second gate electrode, the etching stopper layers, and the first semiconductor layer;

etching the interlayer insulating layer to form a first source contact hole and a first drain contact hole such that the first source contact hole and the first drain contact hole expose the plurality of etching stopper layers, respectively; and

etching the interlayer insulating layer and the gate insulating layer together to form a second source contact hole and a second drain contact hole such that the second source contact hole and a second drain contact hole partially expose the second semiconductor layer.

20. The method as claimed in claim 19 , further comprising forming a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode on the interlayer insulating layer, and wherein:

the first source electrode and the first drain electrode are directly connected to the first semiconductor layer via the first source and first drain contact holes or indirectly connected to the first semiconductor layer via the etching stopper layers, and

the second source electrode and the second drain electrode are connected to the second semiconductor layer through the second source contact hole and the second drain contact hole, respectively.

21. The method as claimed in claim 20 , wherein the etching stopper layers are disposed external to the first semiconductor layer.

22. The method as claimed in claim 20 , wherein the second semiconductor layer includes:

a channel region, the channel region being disposed under the second gate electrode, and

source and drain regions, the source and drain regions being disposed at respective sides of the channel region.

23. The method as claimed in claim 22 , wherein the channel region of the second semiconductor layer includes a non-doped polycrystalline silicon layer and the source and drain regions of the second semiconductor layer include an impurity-doped polycrystalline silicon layer.

24. The method as claimed in claim 23 , wherein the first gate electrode is formed in the same way as, in the same plane as, and of the same material as the source and drain regions of the second semiconductor layer.