Methods and systems for DSP-based receivers
View Patent ↗Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.
1. A method, comprising:
(a) receiving a data signal;
(b) generating N sampling signals, each of said N sampling signals having a respective phase;
(c) sampling said data signal with said N sampling signals to generate N samples;
(d) individually adjusting each of said N sampling signals to reduce one or more of sampling phase errors, gain errors, and offsets in said N samples; and
(e) generating a digital signal representative of said received data signal from said N samples.
2. The method of claim 1 , wherein each of said N samples have a sampling rate lower than a symbol rate of said data signal.
3. The method of claim 1 , wherein said N sampling signals are time-staggered relative to each other.
4. The method of claim 1 , wherein said sampling phase errors are caused by periodic jitter in said N sampling signals.
5. The method of claim 1 , wherein step (b) comprises sampling said data signal with said N sampling signals in respective analog-to-digital converter (ADC) paths.
6. The method of claim 5 , wherein said gain errors are caused by gain mismatches among said ADC paths.
7. The method of claim 1 , wherein said offsets cause offset mismatches among said N samples.
8. The method of claim 1 , wherein step (d) further comprises measuring said offsets in a digital domain and individually adjusting for said offsets in said digital domain for each of said N sampling signals.
9. The method of claim 8 , wherein step (d) further comprises measuring said offsets in an M-path parallel decision feedback equalizer (DFE) and individually adjusting one or more DFE DC taps associated with each of said N sampling signals.
10. The method of claim 1 , wherein step (d) further comprises measuring said offsets in a digital domain and individually adjusting for said offsets in an analog domain for each of said N sampling signals.
11. The method of claim 10 , wherein step (d) further comprises measuring said offsets in an M-path parallel decision feedback equalizer (DFE) and individually adjusting reference voltages of respective analog-to-digital converters associated with each of said N sampling signals.
12. The method of claim 1 , wherein step (d) further comprises measuring said gain errors in a digital domain and individually adjusting for said gain errors in said digital domain for each of said N sampling signals.
13. The method of claim 1 , wherein step (d) further comprises measuring said gain errors in an M-path parallel feed-forward equalizer (FFE) and individually adjusting one or more FFE taps associated with each of said N sampling signals.
14. The method of claim 1 , wherein step (d) further comprises measuring said gain errors in a digital domain and individually adjusting for said gain errors in an analog domain for each of said N sampling signals.
15. The method of claim 1 , wherein step (d) further comprises measuring said sampling phase errors in respective phase detectors and individually adjusting for said sampling phase errors in a timing recovery module for each of said N sampling signals.
16. A receiver, comprising:
a timing recovery module that generates N sampling signals having time-staggered phases;
an analog-to-digital converter (ADC) array of N ADC paths that receives a data signal and that samples said data signal according to said N sampling signals to generate N samples; and
a compensation module configured to individually adjust each of said N ADC paths to reduce one or more of sampling phase errors, gain errors, and offsets in said N samples.
17. The receiver of claim 16 , wherein said compensation module comprises N timing recovery loops, each of said N timing recovery loops coupled to a respective one of said N ADC paths and configured to adjust for a respective sampling phase error in said respective one of said N ADC paths.
18. The receiver of claim 16 , wherein said compensation module comprises an M-path parallel decision feedback equalizer (DFE) having configurable DFE DC taps to adjust for said offsets in said N samples.
19. The receiver of claim 16 , wherein said compensation module comprises a programmable gain amplifier (PGA) array of N PGAs, each of said PGAs coupled to a respective one of said N ADC paths and configured to adjust for a respective gain error in said respective one of said N ADC paths.
20. The receiver of claim 16 , wherein each of said N samples have a sampling rate lower than a symbol rate of said data signal.