Pad area, organic light emitting diode display device having the same, and method of fabricating the same

1 . A pad area, comprising:

a substrate;

a silicon layer pattern arranged on the substrate;

an insulating layer arranged on the silicon layer pattern;

an interconnection layer arranged on the insulating layer; and

a protective layer surrounding an edge of the interconnection layer and having an opening exposing the interconnection layer.

2 . The pad area of claim 1 , wherein the silicon layer pattern, the insulating layer and the interconnection layer have uneven surfaces.

3 . The pad area of claim 1 , wherein the silicon layer pattern is a polycrystalline silicon layer pattern.

4 . An organic light emitting diode (OLED) display device comprising a substrate having a pixel area and a pad area, the pad area comprising:

a silicon layer pattern arranged on the substrate;

an insulating layer arranged on the silicon layer pattern;

an interconnection layer arranged on the insulating layer; and

a protective layer surrounding an edge of the interconnection layer and having an opening exposing the interconnection layer.

5 . The OLED display device of claim 4 , wherein the silicon layer pattern, the insulating layer and the interconnection layer have uneven surfaces.

6 . The OLED display device of claim 4 , wherein the pixel area comprises:

a silicon layer pattern arranged on the substrate and having source and drain regions;

a gate insulating layer arranged on an entire surface of the substrate having the silicon layer pattern;

a gate electrode arranged on the gate insulating layer;

an interlayer insulating layer arranged on the gate electrode; and

source and drain electrodes electrically connected to the source and drain regions respectively of the silicon layer pattern in the pixel area through contact holes arranged in the interlayer insulating layer.

7 . The OLED display device of claim 6 , wherein the insulating layer in the pad area is the gate insulating layer, and the interconnection layer in the pad area is comprised of a same material as that of the gate electrode.

8 . The OLED display device of claim 6 , wherein the insulating layer in the pad area is the interlayer insulating layer, and the interconnection layer in the pad area is comprised of a same material as that of the source and drain electrodes.

9 . The OLED display device of claim 4 , wherein the silicon layer pattern is a polycrystalline silicon layer pattern.

10 . A method of fabricating an organic light emitting diode (OLED) display device, comprising:

providing a substrate having a pixel area and a pad area;

forming an amorphous silicon layer on an entire surface of the substrate;

forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer;

forming polycrystalline silicon layer patterns at predetermined regions of the pixel and pad areas by patterning the polycrystalline silicon layer, the polycrystalline silicon layer pattern in the pixel area having source and drain regions and a channel region;

forming a gate insulating layer on the entire surface of the substrate having the polycrystalline silicon layer patterns;

applying a gate electrode material on the gate insulating layer; and

forming a gate electrode corresponding to the channel region of the polycrystalline silicon layer pattern in the pixel area and an interconnection layer corresponding to the polycrystalline silicon layer pattern in the pad area by patterning the gate electrode material.

11 . The method of claim 10 , wherein the crystallizing the amorphous silicon layer into the polycrystalline silicon layer is performed using a laser.

12 . The method of claim 11 , wherein the crystallizing is performed by an excimer laser annealing (ELA) technique.

13 . The method of claim 10 , wherein the interconnection layer has an uneven surface.

14 . A method of fabricating an OLED display device, comprising:

providing a substrate having a pixel area and a pad area;

forming an amorphous silicon layer on an entire surface of the substrate;

forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer;

forming polycrystalline silicon layer patterns in predetermined regions of the pixel and pad areas respectively by patterning the polycrystalline silicon layer, the polycrystalline silicon layer pattern in the pixel area having source and drain regions;

forming an interlayer insulating layer on the entire surface of the substrate having the polycrystalline silicon layer patterns;

applying a material for source and drain electrodes to the pixel area and the pad area; and

forming the source and drain electrodes electrically connected to the source and drain regions respectively of the polycrystalline silicon layer pattern in the pixel area through contact holes formed in the interlayer insulating layer and forming an interconnection layer corresponding to the polycrystalline silicon layer pattern in the pad area by patterning the material for source and drain electrodes.

15 . The method of claim 14 , wherein the crystallizing the amorphous silicon layer into the polycrystalline silicon layer is performed using a laser.

16 . The method of claim 15 , wherein the crystallizing is performed by an excimer laser annealing technique.