Granted Patent B2

US 8,022,760 · App. 12/809,757 · Granted Sep 20, 2011

Abstract

Claims (25)

1. An electronic device comprising:

an N-way Doherty amplifier with an amplifier input and an amplifier output, wherein:

N is an integer larger than two;

the amplifier has a main stage, and (N−1) peak stages in an ordered arrangement;

the (N−1) peak stages include at least a first peak stage and a second peak stage;

the amplifier has an input network connecting the amplifier input to a first input of the main stage, and to respective inputs of respective ones of the peak stages;

the amplifier has an output network connecting, on one hand, a first output of the main stage, and respective outputs of respective ones of the (N−1) peak stages to the amplifier output, on another hand;

the output network implements a first impedance, as experienced by the main stage, with a first phase shift of 90° between the first output and the amplifier output;

the output network implements a respective further impedance as experienced by a respective one of the (N−1) peak stages, with a respective further phase shift between the output of the respective peak stage and the amplifier output;

each specific one of the further phase shifts for a specific one of the peak stages is larger by 90° than another further phase shift of another one of the peak stages next in the ordered arrangement;

the input network implements a second impedance with a second phase shift of (N−2) times 90° between the amplifier input and the first input of the main stage;

the input network implements a respective additional impedance with a respective one of additional phase shifts between the amplifier input and the respective input of the respective peak stage;

each specific one of the additional phase shifts for a specific one of the peak stages is larger by 90° than the additional phase shift of a previous one of the peak stages in the ordered arrangement; and

the additional phase shift between the amplifier input and the first peak stage is 0°.

2. The device of claim 1 , wherein each respective one of the first impedance, second impedance, further impedances and additional impedances is implemented with a respective quarter-wave transmission line.

3. The device of claim 2 , wherein N equals 3.

4. The device of claim 1 , wherein N equals 3.

5. The device of claim 4 , wherein the output network comprises:

a first capacitor between the first output and signal-ground;

a second capacitor between the second output and signal-ground;

a third capacitor between the third output and signal-ground;

a fourth capacitor between the amplifier output and signal-ground;

a first inductor between the first output and the amplifier output;

a second inductor between the second output and the third output; and

a third inductor between the third output and the amplifier output.

Assignments (13)