IP Library Granted Patent US 8,212,545
Granted Patent B2
US 8,212,545 · App. 12/813,004 · Granted Jul 3, 2012

Reference voltage circuit and electronic device

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Quick Facts
Patent No.
US 8,212,545
App. No.
12/813,004
Granted
Jul 3, 2012
Kind
B2
Abstract

In order to realize a reference voltage circuit that operates with lower current consumption while maintaining an operation at lower voltage without causing deterioration of a power supply rejection ratio, provided is a reference voltage circuit in which a depletion transistor of an ED type reference voltage circuit is constituted of a plurality of depletion transistors connected in series, and in which a gate terminal of a cascode depletion transistor is connected to a connection point between the depletion transistors of the ED type reference voltage circuit.

Claims (25)

1. A reference voltage circuit, comprising:

an enhancement depletion (ED) type reference voltage circuit comprising:

an N-channel depletion type metal oxide semiconductor (MOS) transistor comprising:

a first N-channel depletion type MOS transistor having a source and a gate connected to an output terminal; and

a second N-channel depletion type MOS transistor having a gate connected to the output terminal, and a source connected to a drain of the first N-channel depletion type MOS transistor, and

an N-channel enhancement type MOS transistor comprising a drain and a gate connected to the output terminal, and a source connected to a ground (GND) terminal, and

a cascode circuit disposed between a power supply terminal and the ED type reference voltage circuit,

wherein the N-channel depletion type MOS transistor comprises a plurality of N-channel depletion type MOS transistors connected in series, and

wherein the cascode circuit comprises an N-channel depletion type MOS transistor comprising a third N-channel depletion type MOS transistor having a drain connected to the power supply terminal, and a gate connected to the drain of the first N-channel depletion type MOS transistor and the source of the second N-channel depletion type MOS transistor.

2. A reference voltage circuit according to claim 1 , wherein at least one of the first N-channel depletion type MOS transistor and the second N-channel depletion type MOS transistor comprises a plurality of N-channel depletion type MOS transistors.

3. An electronic device, comprising the reference voltage circuit according to claim 1 .

4. A reference voltage circuit, comprising:

n ED type reference voltage circuits, where n is an integer of 2 or more, each comprising:

an N-channel depletion type MOS transistor comprising:

a first N-channel depletion type MOS transistor having a source and a gate connected to an output terminal; and

a second N-channel depletion type MOS transistor having a gate connected to the output terminal, and a source connected to a drain of the first N-channel depletion type MOS transistor; and

an N-channel enhancement type MOS transistor having a drain and a gate connected to the output terminal, and a source connected to a GND terminal,

n cascode circuits each disposed between a power supply terminal and each of the n ED type reference voltage circuits,

wherein the N-channel depletion type MOS transistor comprises a plurality of N-channel depletion type MOS transistors connected in series,

wherein each of the n cascode circuits comprises an N-channel depletion type MOS transistor,

wherein the N-channel depletion type MOS transistor of an m-th cascode circuit, where m is an integer satisfying 0<m<n, has a gate connected to any one of connection points between the plurality of N-channel depletion type MOS transistors connected in series of an (m+1)-th ED type reference voltage circuit, and

wherein the N-channel depletion type MOS transistor of an n-th cascode circuit has a gate connected to any one of connection points between the plurality of N-channel depletion type MOS transistors connected in series of a first ED type reference voltage circuit,

wherein the N-channel depletion type MOS transistor of each of the n cascade circuits comprises a third N-channel depletion type MOS transistor having a drain connected to the power supply terminal, and a gate connected to the drain of the first N-channel depletion type MOS transistor and the source of the second N-channel depletion type MOS transistor.

5. A reference voltage circuit according to claim 4 , wherein at least one of the first N-channel depletion type MOS transistor and the second N-channel depletion type MOS transistor comprises a plurality of N-channel depletion type MOS transistors.

6. An electronic device, comprising the reference voltage circuit according to claim 4 .

Assignments (5)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2010
From: IMURA, TAKASHI
To: SEIKO INSTRUMENTS INC.
Reel/Frame 024519/0171 →