CMOS input buffer circuit
View Patent ↗Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes: a depletion type NMOS transistor including a drain connected to a power supply terminal (VDD), and a gate connected to an output terminal; a PMOS transistor including a source connected to a source of the depletion type NMOS transistor, a drain connected to the output terminal, and a gate connected to an input terminal; and an NMOS transistor including a source connected to a reference terminal (GND), a gate connected to the input terminal, and a drain connected to the output terminal.
1. A complementary metal oxide semiconductor (CMOS) input buffer circuit for converting a signal lower than CMOS level that is input to an input terminal into a CMOS level signal and outputting the converted CMOS level signal to an output terminal,
the CMOS input buffer circuit comprising:
a power supply terminal (VDD) and a reference terminal (GND) that are each supplied with a CMOS level voltage;
a first depletion type NMOS transistor including:
a drain connected to the power supply terminal (VDD); and
a gate connected to the output terminal;
a first PMOS transistor including:
a source connected to a source of the first depletion type NMOS transistor;
a drain connected to the output terminal; and
a gate connected to the input terminal; and
an NMOS transistor including:
a source connected to the reference terminal (GND);
a gate connected to the input terminal; and
a drain connected to the output terminal
a reference voltage circuit for outputting a reference voltage from a reference voltage output terminal thereof;
a second PMOS transistor including:
a drain connected to the output terminal; and
a gate connected to the input terminal; and
a second depletion type NMOS transistor including:
a drain connected to the power supply terminal (VDD);
a source connected to a source of the second PMOS transistor; and
a gate connected to the reference voltage output terminal.
2. A CMOS input buffer circuit according to claim 1 , further comprising a level shift circuit that is connected between the input terminal and the output terminal of the CMOS input buffer circuit.
3. A CMOS input buffer circuit according to claim 1 , wherein the reference voltage circuit comprises:
a third depletion type NMOS transistor including:
a drain connected to the power supply terminal (VDD);
a gate connected to the reference terminal (GND); and
a source connected to the reference voltage output terminal; and
at least one saturation-connected MOS transistor that is connected between the reference voltage output terminal and the reference terminal (GND).
4. A CMOS input buffer circuit for converting a signal lower than CMOS level that is input to an input terminal into a CMOS level signal and outputting the converted CMOS level signal to an output terminal,
the CMOS input buffer circuit comprising:
a power supply terminal (VDD) and a reference terminal (GND) that are each supplied with a CMOS level voltage;
an NMOS transistor including:
a source connected to the reference terminal (GND);
a gate connected to the input terminal; and
a drain connected to the output terminal;
a first PMOS transistor including:
a source connected to the power supply terminal (VDD); and
a drain connected to the output terminal;
a second PMOS transistor including:
a source connected to the power supply terminal (VDD);
a drain connected to a gate of the first PMOS transistor; and
a gate connected to the output terminal;
a third PMOS transistor including:
a drain connected to the reference terminal (GND); and
a gate connected to the input terminal; and
a first depletion type NMOS transistor including:
a source connected to a source of the third PMOS transistor;
a drain connected to the drain of the second PMOS transistor; and
a gate connected to a reference voltage.
5. A CMOS input buffer circuit according to claim 4 , further comprising a circuit for outputting the reference voltage,
the circuit comprising:
a second depletion type NMOS transistor including:
a drain connected to the power supply terminal (VDD);
a gate connected to the reference terminal (GND); and
a source connected to a reference voltage output terminal of the circuit; and
at least one saturation-connected MOS transistor that is connected between the reference voltage output terminal and the reference terminal (GND).
6. A CMOS input buffer circuit according to claim 4 , wherein the reference voltage comprises a voltage of the reference terminal (GND).
7. A CMOS input buffer circuit for converting a signal lower than CMOS level that is input to an input terminal into a CMOS level signal and outputting the converted CMOS level signal to an output terminal,
the CMOS input buffer circuit comprising:
a power supply terminal (VDD) and a reference terminal (GND) that are each supplied with a CMOS level voltage;
an NMOS transistor including:
a source connected to the reference terminal (GND);
a gate connected to the input terminal; and
a drain connected to the output terminal;
a first PMOS transistor including:
a source connected to the power supply terminal (VDD); and
a drain connected to the output terminal;
a second PMOS transistor including:
a source connected to the power supply terminal (VDD); and
a gate connected to the drain of the NMOS transistor;
a first constant current circuit including:
one terminal connected to a gate of the first PMOS transistor; and
another terminal connected to a drain of the second PMOS transistor;
a second constant current circuit including:
one terminal connected to the input terminal; and
another terminal connected to the reference terminal (GND); and
a depletion type NMOS transistor including:
a source connected to the one terminal of the second constant current circuit;
a drain connected to the gate of the first PMOS transistor; and
a gate connected to the reference terminal (GND).