Method for source synchronous high-speed signal synchronization

1. A source synchronous signal synchronization system, comprising:

a. a differential signal receiver;

b. a tunable input delay element coupled to the receiver;

c. an input serializer/deserializer (ISerDes) coupled to the tunable input delay element;

d. an alignment unit coupled to the ISerDes; and

e. a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit;

wherein the alignment unit comprises a Pseudo-Random Bit Sequence (PRBS) error detector, bit alignment is based on a PRBS pattern, and the PRBS pattern has a predetermined delay, wherein the bit alignment is achieved by tuning the bits to the predetermined delay.

2. The system of claim 1 , wherein data window centering is based on the PRBS pattern.

3. The system of claim 1 , wherein the PRBS pattern has no delay, wherein the bit alignment is achieved by having no delay in the received serial signals.

4. The system of claim 1 , wherein the delay control unit selects a tap from continuous zero error taps.

5. The system of claim 1 , wherein the delay control unit selects a tap with the lowest bit error rate (BER).

6. The system of claim 1 , wherein the system is based on training sequence, and the alignment unit comprises a word aligning block.

7. The system of claim 6 , wherein the word aligning block works with the tunable input delay to reach a statistically constant output.

8. The system of claim 6 , wherein the delay control unit achieves data window centering by searching for a statistically stable period and selecting a middle tap for the statistically constant period.

9. The system of claim 1 , wherein delay tuning is based on one or more bits of the ISerDes.

10. The system of claim 1 , wherein a bit-level alignment is processed after data window centering.

11. The system of claim 1 , wherein a bit-level alignment is achieved by tuning input delay in bit period increment to have taps used for each signal having a predetermined skew range.

12. The system of claim 11 , wherein the bit-level alignment is achieved by tuning an equivalent serial PRBS distance to a predetermined value.

13. The system of claim 12 , wherein the bit-level alignment is checked by having identical outputs on all ISerDes outputs.

14. The system of claim 11 , wherein the bit-level alignment is achieved by a training sequence where each signal has same input.

15. The system of claim 14 , wherein the bit-level alignment is checked by having a different word alignment mode.

16. A source synchronous signal synchronization system, comprising:

a. a differential signal receiver;

b. a tunable input delay element coupled to the receiver;

c. an input serializer/deserializer (ISerDes) coupled to the tunable input delay element;

d. an alignment unit coupled to the ISerDes; and

e. a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit;

wherein the word aligning block works with the tunable input delay to reach a statistically constant output and the system is based on training sequence, and the alignment unit comprises a word aligning block.

17. A source synchronous signal synchronization system, comprising:

f. a differential signal receiver;

g. a tunable input delay element coupled to the receiver;

h. an input serializer/deserializer (ISerDes) coupled to the tunable input delay element;

i. an alignment unit coupled to the ISerDes; and

j. a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit;

wherein the bit-level alignment is achieved by tuning an equivalent serial Pseudo-Random Bit Sequence (PRBS) distance to a predetermined value and a bit-level alignment is achieved by tuning input delay in bit period increment to have taps used for each signal having a predetermined skew range.