IP Library Granted Patent US 9,134,741
Granted Patent B2
US 9,134,741 · App. 12/814,457 · Granted Sep 15, 2015

Dynamic biasing for regulator circuits

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,134,741
App. No.
12/814,457
Granted
Sep 15, 2015
Kind
B2
Abstract

The disclosed invention provides apparatus and methods for dynamic biasing in electronic systems and circuits. The apparatus and methods disclosed provide non-linear biasing responsive to monitored load conditions.

Claims (34)

1. A method for biasing a circuit comprising the steps of:

placing a regulator in the circuit;

providing the regulator with a bias current;

sensing an output current of the circuit;

comparing the sensed output current to a preselected threshold; and

adjusting the bias current using a piecewise linear and non-linear feedback function based on the comparison of the sensed output current with the preselected threshold wherein said adjusted bias current is non-linear with respect to the sensed output current.

2. The method according to claim 1 wherein the step of adjusting the bias current further comprises using a logarithmic function for a portion of the piecewise linear and non-linear feedback function.

3. The method according to claim 1 wherein the step of adjusting the bias current further comprises using a non-linear function that comprises at least one step function for a portion of the piecewise linear and non-linear feedback function.

4. The method according to claim 1 wherein the step of adjusting the bias current further comprises using a continuous piecewise linear and non-linear function.

5. The method according to claim 1 wherein the step of adjusting the bias current further comprises clamping the linear and non-linear function at a maximum value.

6. The method according to claim 1 wherein the step of adjusting the bias current further comprises using a source-degenerated non-linear function for a portion of the piecewise linear and non-linear feedback function.

7. A low-power regulator circuit comprising:

a power input node and a power output node, operably coupling the low-power regulator circuit with an associated system;

a load monitoring component operably coupled for sensing an output current at the output node; and

a biasing component configured for comparing the sensed output current to a preselected threshold, and providing a bias current amplitude that is a linear and non-linear function of the comparison of the sensed output current with the preselected threshold wherein said bias current amplitude is linear and non-linear with respect to the sensed output current.

8. A circuit according to claim 7 wherein the biasing component compares the sensed output current to a plurality of preselected thresholds.

9. A circuit according to claim 7 wherein the biasing component is configured to provide a bias current that is linear based on a first comparison of a first threshold and a first sensed output current, and to provide a bias current that is non-linear based on a second comparison of a second threshold and a second sensed output current.

10. A circuit according to claim 7 wherein the load monitoring component further comprises a current sensing module.

11. A circuit according to claim 7 wherein the biasing component further comprises a threshold detecting module.

12. A circuit according to claim 7 wherein the biasing component further comprises a feedback function module.

13. The low-power regulator circuit of claim 7 wherein the biasing component further comprises:

a current sensing circuit configured to generate a current sense output;

a threshold detection circuit configured to receive the current sense output and to generate a threshold detect output;

a feedback function circuit configured to receive the threshold detect output and to generate a feedback function output;

an amplifier coupled to the power input node, the power output node, a reference voltage and the feedback function circuit; and

a transistor having a first terminal coupled to the power input node, a control terminal coupled to the amplifier and a second terminal coupled to the power output node.

14. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that is linear and a second output range that is non-linear.

15. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that is linear and a continuous second output range that is non-linear.

16. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that is linear and a second output range that is logarithmic.

17. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that is linear and a second output range that is asymptotic.

18. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that is linear and a second output range that is a step function.

19. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that has a first linear response, a second output range that has a second linear response that is different from the first linear response and a third output range that is non-linear.

20. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that has a first linear response, a second output range that has a second linear response that is different from the first linear response and a third output range that is a step function.

21. The low-power regulator of claim 7 wherein the linear and non-linear function comprises a first output range that has a first linear response, a second output range that has a second linear response that is different from the first linear response and a third output range that is logarithmic.

Assignments (4)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (040646/0799) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0544 →
SECURITY INTEREST Recorded Nov 17, 2016
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 040646/0799 →
SECURITY INTEREST Recorded May 28, 2015
From: TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 035732/0326 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2010
From: ATRASH, AMER; TEGGATZ, ROSS; SMITH, BRETT
To: TRIUNE IP LLC
Reel/Frame 024526/0670 →