Active device array substrate
View Patent ↗An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd 1 . In the pixel units adjacent to the nodes, the gate-to-drain capacitances of some active devices are Cgd 2 , the gate-to-drain capacitances of the other active devices are Cgd 1 , and Cgd 1≠ Cgd 2.
1. An active device array substrate comprising:
a substrate;
a plurality of scan lines disposed on the substrate;
a plurality of data lines intersected with the scan lines;
a plurality of scan signal transmission lines intersected with the scan lines, each of the scan signal transmission lines respectively connecting one of the scan lines through a node; and
a plurality of pixel units electrically connected to one of the data lines and one of the scan lines correspondingly, each of the pixel units comprising:
an active device having a gate, a source, and a drain; and
a pixel electrode electrically connected to the drain, a gate-to-drain capacitance of each of the active devices in the pixel units not adjacent to the nodes being Cgd 1 , the gate-to-drain capacitances of parts of the active devices in the pixel units adjacent to the nodes being Cgd 2 , the gate-to-drain capacitances of the other parts of the active devices being Cgd 1 , wherein Cgd 1 ≠Cgd 2 .
2. The active device array substrate as claimed in claim 1 , wherein in the pixel units adjacent to the nodes, a pattern of each of the gates is substantially the same, an area of each of the gates is substantially the same, a pattern of each of the drains is not substantially the same, and an area of each of the drains is not substantially the same.
3. The active device array substrate as claimed in claim 1 , wherein in the pixel units adjacent to the nodes, a pattern of each of the drains is substantially the same, an area of each of the drains is substantially the same, a pattern of each of the gates is not substantially the same, and an area of each of the gates is not substantially the same.
4. The active device array substrate as claimed in claim 1 , wherein in the pixel units not adjacent to the nodes, a pattern of each of the gates is substantially the same, an area of each of the gates is substantially the same, a pattern of each of the drains is substantially the same, and an area of each of the drains is substantially the same.
5. The active device array substrate as claimed in claim 1 , wherein the data lines comprise a plurality of first data lines and a plurality of second data lines alternately arranged, and the pixel units located between any two adjacent first data line and second data line of the first data lines and the second data lines are arranged in two columns.
6. The active device array substrate as claimed in claim 5 , wherein the pixel units comprise a plurality of first pixel units and a plurality of second pixel units, and each of the second pixel units is electrically connected to one of the first data lines or one of the second data lines through one of the first pixel units.
7. The active device array substrate as claimed in claim 6 , wherein in a column direction, the first pixel units located between any two adjacent first data line and second data line of the first data lines and the second data lines and arranged in even rows are aligned to the second pixel units arranged in odd rows, and the first pixel units arranged in odd rows are aligned to the second pixel units arranged in even rows.
8. The active device array substrate as claimed in claim 7 , wherein an n th scan signal transmission line of the scan signal transmission lines is connected to an n th scan line of the scan lines through an n th node of the nodes, one of the first pixel units adjacent to the n th node is connected to the n th scan line and one of the first data lines, another one of the first pixel units adjacent to the n th node is connected to an (n+1) th scan line of the scan lines and one of the second data lines, one of the second pixel units adjacent to the n th node is connected to an (n−1) th scan line of the scan lines and is connected to the n th scan line and one of the first data lines through one of the first pixel units, and another one of the second pixel units adjacent to the n th node is connected to the n th scan line and is connected to the (n+1) th scan line and one of the second data lines through another one of the first pixel units.
9. The active device array substrate as claimed in claim 8 , wherein in the another one of the first pixel units connected to the (n+1) th scan line and the one of the second data lines, a gate-to drain capacitance of the active device in the another one of the first pixel units is Cgd 1 .
10. The active device array substrate as claimed in claim 1 , wherein an n th scan signal transmission line of the scan signal transmission lines is connected to an n th scan line of the scan lines through an n th node of the nodes, parts of the pixel units adjacent to the n th node are connected to the n th scan line, the other parts of the pixel units adjacent to the n th node are connected to an (n−1) th scan line of the scan lines or an (n+1) th scan line of the scan lines, and a gate-to-drain capacitance of the active device in one of the pixel units which is adjacent to the n th node and is connected to the n th scan line is Cgd 2 .
11. An active device array substrate comprising:
a substrate;
a plurality of scan lines disposed on the substrate;
a plurality of data lines intersected with the scan lines;
a plurality of scan signal transmission lines intersected with the scan lines, each of the scan signal transmission lines respectively connecting one of the scan lines through a node; and
a plurality of pixel units electrically connected to one of the data lines and one of the scan lines correspondingly, each of the pixel units comprising:
an active device having a gate, a source, and a drain; and
a pixel electrode electrically connected to the active device, wherein gate-to-drain capacitances of parts of the active devices are different from gate-to-drain capacitances of other parts of the active devices, such that a feed through level between any two pixel electrodes of the pixel electrodes is substantially less than 0.03 volts.
12. The active device array substrate as claimed in claim 11 , wherein in the pixel units adjacent to the nodes, a pattern of each of the gates is substantially the same, an area of each of the gates is substantially the same, a pattern of each of the drains is not substantially the same, and an area of each of the drains is not substantially the same.
13. The active device array substrate as claimed in claim 11 , wherein in the pixel units adjacent to the nodes, a pattern of each of the drains is substantially the same, an area of each of the drains is substantially the same, a pattern of each of the gates is not substantially the same, and an area of each of the gates is not substantially the same.
14. The active device array substrate as claimed in claim 11 , wherein in the pixel units not adjacent to the nodes, a pattern of each of the gates is substantially the same, an area of each of the gates is substantially the same, a pattern of each of the drains is substantially the same, and an area of each of the drains is substantially the same.
15. The active device array substrate as claimed in claim 11 , wherein the data lines comprise a plurality of first data lines and a plurality of second data lines alternately arranged, and the pixel units located between any two adjacent first data line and second data line of the first data lines and the second data lines are arranged in two columns.
16. The active device array substrate as claimed in claim 15 , wherein the pixel units comprise a plurality of first pixel units and a plurality of second pixel units, and each of the second pixel units is electrically connected to one of the first data lines or one of the second data lines through one of the first pixel units, wherein in a column direction, the first pixel units located between any two adjacent first data line and second data line of the first data lines and the second data lines and arranged in even rows are aligned to the second pixel units arranged in odd rows, and the first pixel units arranged in odd rows are aligned to the second pixel units arranged in even rows, wherein an n th scan signal transmission line of the scan signal transmission lines is connected to an n th scan line of the scan lines through an n th node of the nodes, one of the first pixel units adjacent to the n th node is connected to the n th scan line and one of the first data lines, another one of the first pixel units adjacent to the n th node is connected to an (n+1) th scan line of the scan lines and one of the second data lines, one of the second pixel units adjacent to the n th node is connected to an (n−1) th scan line of the scan lines and is connected to the n th scan line and one of the first data lines through one of the first pixel units, and another one of the second pixel units adjacent to the n th node is connected to the n th scan line and is connected to the (n+1) th scan line and one of the second data lines through another one of the first pixel units, and wherein in the another one of the first pixel units connected to the (n+1) th scan line and the one of the second data lines, a gate-to drain capacitance of the active device in the another one of the first pixel units is Cgd 1 .
17. The active device array substrate as claimed in claim 11 , wherein an n th scan signal transmission line of the scan signal transmission lines is connected to an n th scan line of the scan lines through an n th node of the nodes, parts of the pixel units adjacent to the n th node are connected to the n th scan line, the other parts of the pixel units adjacent to the n th node are connected to an (n−1) th scan line of the scan lines or an (n+1) th scan line of the scan lines, and a gate-to-drain capacitance of the active device in one of the pixel units which is adjacent to the n th node and is connected to the n th scan line is Cgd 2 .