Device for real-time streaming of two or more streams in parallel to a solid state memory device array
View Patent ↗Device for real-time streaming to an array of solid state memory device sets, said device comprising receiving means for receiving data from data streams of individual data rate in parallel, an input cache for buffering received data, a bus system for transferring data from the input buffer to the solid state memory device sets, and a controller adapted for using a page-receiving-time t_r, a page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling the bus system such that data received from the first data stream is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from the at least a second data stream is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only.
1. Device for real-time streaming to an array of solid state memory device sets, each set comprising n parallel addressable solid state memory devices wherein each solid state memory device comprises one or more solid state memory units each comprising a page buffer configured for buffering a data amount p during a page-receiving-time t_r and each solid state memory unit is configured for writing said data amount p from the page buffer to the solid state memory during a page-writing-time wrt_tm, said device for real-time streaming comprising
receiving means for receiving data from at most k data streams in parallel, each data stream being received with an individual data rate and receiving the at most k data streams in parallel results in a data rate of receiving which equals the cumulated individual data rates, an input cache for buffering received data,
a bus system of n parallel buses configured for transferring data from the input cache to the solid state memory device sets, and
a controller for controlling the bus system such that data received from a first data stream of the data streams received in parallel is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from at least a second data stream of the data streams received in parallel is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only, wherein
the controller is further configured for using the page-receiving-time t_r, the page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling to which one of the solid state memory device sets the bus system is transferring data.
2. The device of claim 1 , wherein the bus system is configured for accessing the solid state memory device sets sequentially and the controller is configured for determining, for a currently accessed memory device set,
whether page-writing time has elapsed since last transfer of data to the currently accessed memory device set,
if so, whether the currently accessed memory device set belongs to the first or the second subset,
whether received data accumulated in the input cache from the data stream corresponding to the determined subset amounts to at least one page,
if so, the controller causes the bus system to transfer one page of data accumulated in the input cache from the corresponding data stream to the currently accessed memory device set, and otherwise,
the controller causes the bus system to access the next solid state memory device set in the sequence.
3. Bus control method for controlling a bus system of a real-time streaming device, said bus system being configured for transferring data from an input cache to an array of solid state memory device sets for streaming two or more data streams to the solid state memory device set array wherein the solid state memory device set are accessed by the bus sequentially, said method comprises
determining, for a currently accessed solid state memory device set, whether page-writing time has elapsed since last transfer of data to the accessed memory device set,
if so, determining whether the currently accessed memory device set belongs to a first or the second subset of said array of solid state memory device sets wherein said first subset is designated for storing a first data stream and said second subset is designated for storing at least a second data stream,
determining whether received data accumulated in the buffer input cache from the data stream to which the determined subset is designated amounts to at least one page,
only if so, causing the bus system to transfer at least one page of data accumulated in the input cache from the data stream to which the determined subset is designated to the currently accessed solid state memory device set, and
causing the bus system to access the next solid state memory device set.