IP Library Patent Application 12815661
Patent Application
App. No. 12/815,661

HIERARCHICALLY STRUCTURED MASS STORAGE DEVICE AND METHOD

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Patent No.
US None
App. No.
12/815,661
Abstract

A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices. The first and second non-volatile memory devices have properties including access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices. Desired data storage localities on the storage arrays are determined through access patterns and selectively utilizing the properties of the memory devices to match the data storage requirements.

Claims (39)

1 . A mass storage system comprising:

a mass storage memory drive;

control logic on the mass storage memory drive and comprising a controller and means for executing a hierarchical storage management technique;

a volatile memory cache configured to be accessed by the control logic; and

first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices;

wherein the first and second non-volatile memory devices have properties comprising access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices.

2 . The mass storage system of claim 1 , wherein the hierarchical storage management technique is adapted to monitor the frequency of all requests of data and has a predetermined threshold for the monitored request frequencies, exceeding the request frequency threshold will result in prioritizing the requested data, and the prioritized data are copied from the second non-volatile storage array into the first non-volatile storage array.

3 . The mass storage system of claim 2 , wherein a copy of a file from the second non-volatile storage array to the first non-volatile storage array uses the volatile cache.

4 . The mass storage system of claim 2 , wherein the hierarchical storage management technique is adapted to determine de-prioritizing of data when a request frequency drops below the predetermined frequency.

5 . The mass storage system of claim 4 , wherein the hierarchical storage management technique is adapted to use a checksum comparison or a file time stamp to determine whether a file in the first non-volatile storage array has been modified and, if the file has been modified, writing the modified file back to the second non-volatile storage array.

6 . The mass storage system of claim 5 wherein, if the file in the first non-volatile storage array has not been changed, the file is purged from the first non-volatile storage array without writing it back to the second non-volatile storage array.

7 . The mass storage system of claim 1 , wherein the executing means is configured to adapt to usage patterns to prioritize data distribution to the first and second non-volatile storage arrays.

8 . The mass storage system of claim 1 , wherein the first and second non-volatile memory devices comprise solid-state, microelectromechanical, or nanoelectromechanical memory devices.

9 . The mass storage system of claim 1 , wherein the first and second non-volatile memory devices comprise solid-state memory devices.

10 . The mass storage system of claim 1 , wherein the first non-volatile memory devices are PCM devices, nV SRAM, ferromagnetic or NOR memory devices and the second non-volatile memory devices are NAND or NOR memory devices.

11 . The mass storage system of claim 1 , wherein the volatile memory cache is located on the mass storage memory drive.

12 . The mass storage system of claim 1 , wherein the volatile memory cache is not located on the mass storage memory drive.

13 . The mass storage system of claim 1 , wherein the drive is a direct interface device.

14 . The mass storage system of claim 13 , wherein the direct interface device is a PCIe expansion card.

15 . The mass storage system of claim 1 , wherein the first non-volatile storage array has a wider data path than the second non-volatile storage array.

16 . A method of using the mass storage system of claim 1 , the method comprising:

operating the control logic and executing means to execute the hierarchical storage management technique and store data on the first and second non-volatile storage arrays, the operating step comprising determining through an access pattern a locality on one of the first and second non-volatile storage arrays for storing the data thereon by utilizing the properties of the first and second non-volatile memory devices to match storage requirements of the data;

writing the data to the locality on the first or second non-volatile storage array.

17 . The method of claim 16 , wherein the hierarchical storage management technique monitors the frequency of all requests of data and has a predetermined threshold for the monitored request frequencies, exceeding the request frequency threshold results in prioritizing the requested data, and the prioritized data are copied from the second non-volatile storage array into the first non-volatile storage array.

18 . The method of claim 17 , wherein a copy of a file from the second non-volatile storage array to the first non-volatile storage array uses the volatile cache.

19 . The method of claim 17 , wherein the hierarchical storage management technique determines de-prioritizing of data when a request frequency drops below the predetermined frequency.

20 . The method of claim 19 , wherein the hierarchical storage management technique uses a checksum comparison or a file time stamp to determine whether a file in the first non-volatile storage array has been modified and, if the file has been modified, writing the modified file back to the second non-volatile storage array.

21 . The method of claim 20 wherein, if the file in the first non-volatile storage array has not been changed, the file is purged from the first non-volatile storage array without writing it back to the second non-volatile storage array.

22 . The method of claim 16 , wherein the executing means adapts to usage patterns to prioritize data distribution to the first and second non-volatile storage arrays.

23 . The method of claim 16 , wherein the first and second non-volatile memory devices comprise solid-state, microelectromechanical, or nanoelectromechanical memory devices.

24 . The method of claim 16 , wherein the first non-volatile memory devices are PCM devices, nV SRAM, ferromagnetic or NOR memory devices and the second non-volatile memory devices are NAND or NOR memory devices.

25 . A computer in which the mass storage system of claim 1 is installed and performs the method of claim 16 .

26 . A mass storage system comprising:

a mass storage memory drive configured as a direct interface device;

control logic on the mass storage memory drive and comprising a controller and means for executing a hierarchical storage management technique;

a volatile memory cache configured to be accessed by the control logic; and

first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices;

wherein the first and second non-volatile memory devices have properties comprising access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices.

27 . The mass storage system of claim 26 , wherein the direct interface device is a PCIe expansion card.

Assignments (9)
CHANGE OF NAME Recorded Jun 6, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 033104/0287 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 033051/0626 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Jun 6, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 033102/0550 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Jun 6, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 033102/0781 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2010
From: SCHUETTE, FRANZ MICHAEL; ALLEN, WILLIAM J.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 024695/0495 →