Thin film transistor substrate including disconnection prevention member
View Patent ↗A thin film transistor array panel including a display area having a gate line, a data line insulated from and intersecting the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, and a peripheral area formed on the circumference of the display area, according to an exemplary embodiment of the present invention, includes: a driving signal line formed with the same layer as the gate line in the peripheral area and receiving an external signal; a connection signal line formed with the same layer as the data line in the peripheral area; a disconnection prevention member overlapping the side surface of the connection signal line on the connection signal line; and a connection assistance member formed on the disconnection prevention member and connecting the driving signal line and the connection signal line.
1. A thin film transistor array panel, comprising:
a display area comprising:
a gate line;
a data line insulated from and crossing the gate line;
a thin film transistor connected to the gate line and the data line;
a pixel electrode connected to the thin film transistor; and
a peripheral area disposed on the periphery of the display area and comprising:
a driving signal line formed from the same layer of material as the gate line and configured to receive an external signal;
a gate insulating layer disposed on the driving signal line;
a connection signal line disposed on the gate insulating layer and formed from the same layer of material as the data line;
a disconnection prevention member overlapping a first side surface of the connection signal line; and
a connection assistance member disposed on the disconnection prevention member and connecting the driving signal line and the connection signal line,
wherein the first side surface of the connection signal line has a reverse-tapered etching profile.
2. The thin film transistor array panel of claim 1 , further comprising a color filter disposed under the pixel electrode,
wherein the disconnection prevention member comprises the same type of material as the color filter.
3. The thin film transistor array panel of claim 1 , further comprising a black matrix disposed in the peripheral area,
wherein the disconnection prevention member comprises the same material as the black matrix.
4. The thin film transistor array panel of claim 3 , further comprising a color filter disposed under the pixel electrode.
5. The thin film transistor array panel of claim 1 , further comprising a shift register disposed between the connection signal line and the gate line thereby connecting the connection signal line and the gate line, and configured to output a gate signal to the gate line in response to a signal received from the connection signal line.
6. The thin film transistor array panel of claim 5 , wherein the driving signal line comprises first, second, and third signal lines configured to transmit a power voltage, a first clock signal, and a second clock signal having a different phase than the first clock signal.
7. The thin film transistor array panel of claim 6 , wherein the connection signal line connects at least one of the first, second, and third signal lines to the shift register.
8. The thin film transistor array panel of claim 6 , wherein the driving signal line further comprises a fourth signal line operable to transmit an initialization signal.
9. The thin film transistor array panel of claim 8 , wherein the connection signal line connects at least one of the first, second, third, and fourth signal lines to the shift register.
10. The thin film transistor array panel of claim 1 , wherein the connection assistance member comprises the same material as the pixel electrode.
11. The thin film transistor array panel of claim 1 , wherein the connection assistance member connects the driving signal line and the connection signal line through a plurality of contact holes in the gate insulating layer and the passivation layer.
12. The thin film transistor array panel of claim 11 , wherein the disconnection prevention member comprises a contact hole.
13. The thin film transistor array panel of claim 11 , further comprising a capping layer disposed between the disconnection prevention member and the connection assistance member.
14. The thin film transistor array panel of claim 13 , wherein the capping layer comprises a contact hole.
15. The thin film transistor array panel of claim 1 , further comprising a capping layer disposed between the disconnection prevention member and the connection assistance member.
16. The thin film transistor array panel of claim 15 , wherein the connection assistance member is disposed directly on the capping layer.
17. The thin film transistor array panel of claim 1 , wherein a second side surface of the signal connection line has a tapered etching profile.
18. The thin film transistor array panel of claim 17 , wherein the first and second side surfaces oppose one another on the signal connection line.