Semiconductor device with pads overlapping wiring layers including dummy wiring
View Patent ↗A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
1. A semiconductor device, comprising:
a semiconductor substrate;
an isolation portion formed over the semiconductor substrate;
a plurality of semiconductor regions formed in the semiconductor substrate, each surrounded with the isolation portion;
a plurality of first wirings formed over the semiconductor regions;
a plurality of first dummy wirings formed of a same layer as that of the first wirings;
a plurality of second wirings formed over the first wirings;
a plurality of second dummy wirings formed of a same layer as that of the second wirings; and
a plurality of pads formed over the second wirings and the second dummy wirings,
wherein the first dummy wirings and the second dummy wirings are in a floating state, and
wherein a respective one of the semiconductor regions, a respective one of the first wirings, a respective one of the first dummy wirings, a respective one of the second wirings and a respective one of the second dummy wirings are formed under each of the pads in a plan view.
2. A semiconductor device according to claim 1 ,
wherein each of the semiconductor regions is a protective element for preventing electrostatic breakdown.
3. A semiconductor device according to claim 2 ,
wherein each protective element is a p-n junction diode.
4. A semiconductor device according to claim 1 ,
wherein each of the pads is formed in an uppermost wiring layer.
5. A semiconductor device according to claim 1 ,
wherein a first insulating film is formed over the pads, the first insulating film having a plurality of opening portions;
wherein a plurality of bump electrodes are formed over the pads, each of the bump electrodes being connected to a respective one of the pads via a respective one of the opening portions.
6. A semiconductor device according to claim 5 ,
wherein each of the bump electrodes includes a gold film and an underlying metal film formed under the gold film.
7. A semiconductor device according to claim 5 ,
wherein the semiconductor substrate is of a rectangular shape having a first long side, a second long side, a first short side and a second short side, and
wherein each of the bump electrodes is arranged along the first long side of the semiconductor substrate.
8. A semiconductor device according to claim 7 ,
wherein the semiconductor device has a circuit for driving a liquid crystal display.
9. A semiconductor device according to claim 5 ,
wherein each of the bump electrodes is electrically connected to a respective one of the first wirings, a respective one of the second wirings and a respective one of the semiconductor regions.