Hardware multithreading systems and methods
View Patent ↗According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substrates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities. A hardware thread profiler including global, run and wait profiler registers is used to monitor thread performance to facilitate software development.
1. A multithreaded microcontroller comprising:
a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads;
thread control logic connected to the set of multithreading registers, comprising:
thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and
thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions; and
a thread profiler which collects thread profiling data including at least one of: a thread state transition count and a time period spent by a thread in a set of thread states.
2. The multithreaded microcontroller of claim 1 , wherein:
the set of multithreading registers further includes a plurality of thread register sets; each thread register set corresponds to a thread from the plurality of threads; and said each thread register set comprises a thread priority field identifying a priority of the thread.
3. The multithreaded microcontroller of claim 1 , wherein the set of multithreading registers further includes a microcontroller main state register comprising:
a call code field identifying a type for an event that has caused an entry into a system thread; and
a calling thread identification field identifying a calling thread causing the entry into the system thread.
4. The multithreaded microcontroller of claim 1 , wherein the set of multithreading registers comprises a plurality of mutex registers storing a plurality of mutex states for a corresponding plurality of mutexes.
5. A multithreaded microcontroller comprising:
a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads;
thread control logic connected to the set of multithreading registers, comprising:
thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and
thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions,
wherein the thread state transition logic comprises logic configured to:
transition a state of a thread from a ready state to a run state when the thread is scheduled for execution;
transition the state of the thread from the run state to an interrupt wait state when the thread receives an interrupt;
transition the state of the thread from the run state to a condition wait state when the thread executes a wait condition instruction;
transition the state of the thread from the run state to a mutex wait state when the thread executes a lock mutex instruction;
transition the state of the thread from the run state to an wait instruction cache state when the thread receives an instruction cache miss signal; and
transition the state of the thread from the run state to a wait memory state when the thread receives a data miss signal.
6. A multithreaded data processing method comprising:
storing a plurality of thread states for a corresponding plurality of threads in a set of thread state registers;
controlling thread state transitions for the plurality of threads using thread state transition logic connected to the set of thread state registers; and
executing a set of multithreading system call machine code instructions using thread instructions execution logic connected to the set of thread state registers;
collecting thread profiling data including at least one of: a thread state transition count and a time period spent by a thread in a set of thread states.
7. A multithreaded data processing method comprising:
storing a plurality of thread states for a corresponding plurality of threads in a set of thread state registers;
controlling thread state transitions for the plurality of threads using thread state transition logic connected to the set of thread state registers; and
executing a set of multithreading system call machine code instructions using thread instructions execution logic connected to the set of thread state registers,
further comprising:
transitioning a state of a thread from a ready state to a run state when the thread is scheduled for execution;
transitioning the state of the thread from the run state to an interrupt wait state when the thread receives an interrupt;
transitioning the state of the thread from the run state to a condition wait state when the thread executes a wait condition instruction;
transitioning the state of the thread from the run state to a mutex wait state when the thread executes a lock mutex instruction;
transitioning the state of the thread from the run state to an wait instruction cache state when the thread receives an instruction cache miss signal; and
transitioning the state of the thread from the run state to a wait memory state when the thread receives a data miss signal.
8. The multithreaded data processing method of claim 6 , wherein the set of multithreading system call machine code instructions includes a set of mutex locking instructions.
9. The multithreaded data processing method of claim 6 , wherein the set of multithreading system call machine code instructions includes a wait condition instruction.
10. The multithreaded data processing method of claim 9 , wherein executing the wait condition instruction comprises checking a mutex register to determine whether a mutex identified by the wait condition instruction is locked by a thread executing the wait condition instruction.
11. The multithreaded data processing method of claim 9 , wherein executing the wait condition instruction comprises transitioning a state of a thread executing the wait condition instruction from a run state to a condition wait state.
12. The multithreaded data processing method of claim 6 , wherein the set of multithreading system call machine code instructions includes a condition signal instruction.
13. The multithreaded data processing method of claim 12 , wherein executing the condition signal instruction comprises transitioning a state of a thread waiting for a condition signal from a condition wait state to a ready state.
14. The multithreaded data processing method of claim 6 , further comprising scheduling the plurality of threads for execution according to the plurality of thread states and a corresponding plurality of thread priorities.
15. The multithreaded data processing method of claim 6 , further comprising collecting thread profiling data for the plurality of threads.
16. A multithreaded microcontroller comprising:
an instruction fetching unit configured to receive a set of machine-code instructions for a plurality of threads, the set of instructions including a set of arithmetic and logical instructions, and a set of multithreading system call instructions;
an arithmetic logic unit connected to the instruction fetching unit and configured to receive and execute the set of arithmetic and logical instructions;
a hardware thread controller connected to the instruction fetching unit and the arithmetic logic unit, configured to receive and execute the set of multithreading system call instructions according to a plurality of thread states that are associated with the plurality of threads; and
a thread profiler which collects thread profiling data including at least one of: a thread state transition count and a time period spent by a thread in a set of thread states.
17. The multithreaded microcontroller of claim 16 , wherein the set of multithreading system calls comprises a mutex locking instruction, and the thread control logic comprises mutex locking execution logic configured to execute the mutex locking instruction.
18. The multithreaded microcontroller of claim 17 , wherein the thread controller comprises thread scheduling logic configured to schedule a plurality of threads according to the thread states and a corresponding plurality of thread priorities.
19. The multithreaded microcontroller of claim 17 , wherein the thread controller comprises a thread profiler configured to collect thread profiling data for the plurality of threads.
20. The multithreaded microcontroller of claim 19 , wherein the thread profiling data includes a set of state transition counts.