Thin film display panel and method of manufacturing the same
View Patent ↗A thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer disposed on the gate line; an semiconductive oxide layer disposed on the gate insulating layer; a data line disposed on the semiconductive oxide layer and including a source electrode; a drain electrode facing the source electrode on the semiconductive oxide layer; and a passivation layer disposed on the data line. The semiconductive oxide layer is patterned with chlorine (Cl) containing gas which alters relative atomic concentrations of primary semiconductive characteristic-providing elements of the semiconductive oxide layer at least at a portion where a transistor channel region is defined.
1. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate line having a gate electrode extending therefrom on a light passing substrate;
forming a gate insulating layer, a semiconductive oxide layer, a data line metal layer, and a patterned photoresist film on the gate line having the gate electrode; and
etching the data line metal layer and the semiconductive oxide layer to form a source electrode and a drain electrode spaced apart by a channel region formed between the source electrode and the drain electrode,
wherein the etching the data line metal layer on the channel region uses fluorine containing gas, and
wherein the etching the semiconductive oxide layer on the channel region uses chlorine containing gas.
2. The method of claim 1 ,
wherein the fluorine containing gas is SF6/O2, and
wherein the chlorine containing gas is Cl2/O2.
3. The method of claim 2 , wherein the forming a semiconductive oxide layer comprises forming a GIZO layer or a XIZO layer.
4. The method of claim 3 , wherein the etching the semiconductive oxide layer comprises etching the semiconductive oxide layer less than about 150 angstroms.
5. The method of claim 2 , wherein the etching the semiconductive oxide layer comprises etching the semiconductive oxide layer less than about 150 angstroms.
6. The method of claim 1 , wherein the forming a data line metal layer comprises using at least one of Mo, Al, Cu, Ti, Mn, or respective alloys thereof.
7. The method of claim 1 , wherein the forming a semiconductive oxide layer comprises forming a GIZO layer or a XIZO layer.
8. The method of claim 7 , wherein the etching the semiconductive oxide layer comprises etching the semiconductive oxide layer less than about 150 angstroms.
9. The method of claim 7 , wherein the data line metal layer comprises at least one of Mo, Al, Cu, Ti, Mn, and alloys thereof.
10. The method of claim 1 , wherein the data line metal layer has a multi-layered conductors structure.
11. The method of claim 1 , wherein the gate line and the gate electrode have a double-layered structure.
12. The method of claim 1 , wherein the fluorine containing gas is a mixture of SF6/O2 and Cl2/O2, and
wherein the chlorine containing gas is Cl2/O2.
13. The method of claim 12 , wherein the forming a semiconductive oxide layer comprises forming a GIZO layer or a XIZO layer.
14. The method of claim 13 , wherein the etching the semiconductive oxide layer comprises etching the semiconductive oxide layer less than about 150 angstroms.
15. The method of claim 12 , wherein the etching the semiconductive oxide layer comprises etching the semiconductive oxide layer less than about 150 angstroms.
16. The method of claim 1 , wherein the etching the data line metal layer comprises:
etching the data line metal layer using a gas including SF6/O2 and Cl2/O2, and
etching the data line metal layer using a gas including a fluorine containing gas.
17. The method of claim 16 , wherein the forming a semiconductive oxide layer comprises forming a GIZO layer or a XIZO layer.
18. The method of claim 16 , wherein the gas including a fluorine containing gas is SF6/O2.
19. The method of claim 16 , wherein the etching the semiconductive oxide layer comprises etching the semiconductive oxide layer less than about 150 angstroms.
20. The method of claim 19 , wherein the forming a semiconductive oxide layer comprises forming a GIZO layer or a XIZO layer.