Thin film transistor array panel and manufacturing method thereof
View Patent ↗A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.
1. A manufacturing method for a thin film transistor array panel, comprising:
forming a gate electrode;
forming an insulating layer on the gate electrode;
forming a lower conducting layer and an upper conducting layer on the insulating layer;
etching the upper conducting layer to form a first source electrode and a first drain electrode;
etching the lower conducting layer to form the second source electrode and the second drain electrode;
over-etching the second source electrode and the second drain electrode; and
forming an organic semiconductor between the second source electrode and the second drain electrode.
2. The manufacturing method of claim 1 , further comprising:
forming a bank having a first opening on the first source electrode and the first drain electrode, and
wherein the formation of organic semiconductor is performed by dripping an organic semiconductor solution through the first opening.
3. The manufacturing method of claim 2 , further comprising:
forming a second opening exposing the gate electrode in the insulating layer.
4. The manufacturing method of claim 3 , wherein the formation of the second opening is performed by over-etching the insulating layer.
5. The manufacturing method of claim 4 , further comprising:
forming a gate insulator in the second opening.
6. The manufacturing method of claim 5 , further comprising:
forming a passivation layer in the first opening.
7. A manufacturing method for a thin film transistor array panel, comprising:
forming a gate electrode;
forming an insulating layer on the gate electrode;
forming a lower conducting layer and an upper conducting layer on the insulating layer;
etching the upper conducting layer to form a first source electrode and a first drain electrode;
etching the lower conducting layer to form the second source electrode and the second drain electrode;
over-etching the insulating layer to form a first opening exposing the gate electrode;
forming a bank having a second opening exposing a portion of the first opening on the first source electrode and the first drain electrode; and
forming a gate insulator in the first opening.
8. The method of claim 7 , further comprising:
over-etching the second source electrode and the second drain electrode; and
forming an organic semiconductor between the second source electrode and the second drain electrode.
9. The method of claim 8 , further comprising:
forming a passivation layer in the second opening.