Low noise class AB linearized transconductor
View Patent ↗A transconductor stage is a linearized class AB amplifier having embedded noise filtering that enables a biasing of an in-phase/quadrature (I/Q) modulator core with a low quiescent current. Linearization of the transconductor stage is increased by introducing a small amount of negative feedback into the transconductor stage via a feedback circuitry and an error amplifier. A dominant open loop pole in a path between the error amplifier and an output stage of the transconductor stage forms a dominant pole low-pass filter. A low-pass filter transfer function created when a loop including the feedback circuitry is closed attenuates noise introduced by baseband circuitry that supplies baseband signals to the transconductor stage. A master output stage biases a plurality of slave output stages that are in parallel with the master output stage. Each slave output stage is coupled to an individual modulator core such as a Gilbert cell mixer core.
1. A transconductor stage comprising:
a master output stage having differential inputs, differential outputs, and feedback outputs, wherein the master output stage is biased for class AB amplifier operation;
a feedback circuitry having differential inputs and differential outputs, wherein the differential inputs of the feedback circuitry are coupled to the feedback outputs of the master output stage;
an error amplifier having baseband inputs, feedback inputs, and differential outputs, wherein the feedback inputs of the error amplifier are coupled to the differential outputs of the feedback circuitry; and
a dominant pole low-pass filter having differential inputs and differential outputs, wherein the differential inputs of the dominant pole low-pass filter are coupled to the differential outputs of the error amplifier, and the differential outputs of the dominant pole low-pass filter are coupled to the differential inputs of the master output stage.
2. The transconductor stage of claim 1 further including at least one slave output stage coupled to the differential outputs of the master output stage, wherein the at least one slave output stage is biased for class AB amplifier operation.
3. The transconductor stage of claim 2 wherein the at least one slave output stage is adapted to drive an individual modulator core.
4. The transconductor stage of claim 3 wherein the individual modulator core is a Gilbert cell mixer core.
5. The transconductor stage of claim 2 further including at least one switch for the at least one slave output stage for enabling and disabling the at least one slave output stage.
6. The transconductor stage of claim 5 further including a switch controller for controlling a switch state of the at least one switch for the at least one slave output stage.
7. The transconductor stage of claim 2 wherein the master output stage and the at least one slave output stage comprise field effect transistors (FETs) that are biased with a constant common-mode gate-to-source voltage (V gs ).
8. The transconductor stage of claim 7 wherein the FETs substantially follow a square law characteristic when operated in a saturated region.
9. The transconductor stage of claim 7 wherein the error amplifier and the feedback circuitry provide just enough negative feedback that a predetermined adjacent channel leakage ratio (ACLR) requirement is just met.
10. The transconductor stage of claim 7 wherein a gain of the negative feedback is around 10 dB.
11. The transconductor stage of claim 7 wherein the dominant pole low-pass filter has a dominant pole of around 3 MHz.
12. The transconductor stage of claim 11 wherein the dominant pole low-pass filter has a closed loop bandwidth of around 10 MHz.
13. The transconductor stage of claim 1 further including a single pole low-pass filter having baseband inputs and baseband outputs wherein the baseband outputs of the single pole low-pass filter are coupled to the baseband inputs of the error amplifier.
14. The transconductor stage of claim 13 further including a resistive digital step attenuator having baseband inputs and baseband outputs, wherein the baseband outputs of the resistive digital step attenuator are coupled to the baseband inputs of the single pole low-pass filter.
15. The transconductor stage of claim 14 wherein a differential branch of the resistive digital step attenuator includes a plurality of series resistors with tap points between pairs of the plurality of series resistors, and wherein a first series branch including a first resistor and a first switch is coupled to each of the tap points between the pairs of the plurality of series resistors.
16. The transconductor stage of claim 15 further including a switchable shunt capacitor coupled to the tap points between the pairs of the plurality of series resistors of the differential branch of the resistive digital step attenuator.
17. A mobile terminal comprising:
a modulator to modulate a carrier signal; and
a transconductor stage for driving the modulator comprising:
a master output stage having differential inputs, differential outputs, and feedback outputs, wherein the master output stage is biased for class AB amplifier operation;
a feedback circuitry having differential inputs and differential outputs, wherein the differential inputs of the feedback circuitry are coupled to the feedback outputs of the master output stage;
an error amplifier having baseband inputs, feedback inputs, and differential outputs, wherein the feedback inputs of the error amplifier are coupled to the differential outputs of the feedback circuitry; and
a dominant pole low-pass filter having differential inputs and differential outputs, wherein the differential inputs of the dominant pole low-pass filter are coupled to the differential outputs of the error amplifier, and the differential outputs of the dominant pole low-pass filter are coupled to the differential inputs of the master output stage.
18. The mobile terminal of claim 17 further including at least one slave output stage coupled to the differential outputs of the master output stage, wherein the at least one slave output stage is biased for class AB amplifier operation.
19. The mobile terminal of claim 18 wherein the master output stage and the at least one slave output stage comprise FETs that are biased with a constant common-mode V gs .
20. The mobile terminal of claim 19 wherein the FETs substantially follow a square law characteristic when operated in a saturated region.